EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 97

• Manufacturer Part Number: EP3C40F484C8N
• Description: IC CYCLONE III FPGA 40K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 331
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2475
• Family Type: Cyclone III
• No. Of I/o's: 331
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2492

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Chapter Revision History
Chapter Revision History
Table 5–11. Chapter Revision History (Part 1 of 2)
© December 2009
December 2009
July 2009
June 2009
October 2008
May 2008
September 2007
Date
Altera Corporation
Table 5–11
Version
3.2
3.1
3.0
2.1
2.0
1.2
lists the revision history for this chapter.
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
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Updated chapter part number.
Updated “Clock Networks” on page 5–1.
Updated Table 5–1 on page 5–2, Table 5–3 on page 5–9.
Updated “PLLs in the Cyclone III Device Family” on page 5–9.
Updated “PLL Reconfiguration Hardware Implementation” on page 5–25.
Updated “Spread-Spectrum Clocking” on page 5–32.
Updated the “Dynamic Phase Shifting” and “Introduction” sections.
Updated Figure 5–2, Figure 5–8, and Figure 5–24.
Updated chapter to new template.
Updated Figure 5–2 and added (Note 3).
Updated “clkena Signals” section.
Updated Figure 5–8 and added (Note 3).
Updated “PLL Control Signals” section.
Updated “PLL Cascading” section.
Updated “Cyclone III PLL Hardware Overview” section.
Updated Table 5–6, Table 5–3, Table 5–7.
Updated Figure 5–14.
Updated “PLL Cascading” section.
Updated “Clock Multiplication and Division” section.
Updated Step 6–32 in “PLL Reconfiguration Hardware Implementation” section.
Updated “Spread-Spectrum Clocking” section.
Updated Figure 5–29.
Updated “VCCD and GND” section.
Added “Power Consumption” section.
Updated “Board Layout” section and removed Figure 5-30.
Changes Made
Cyclone III Device Handbook, Volume 1
5–33