EP3C40F484C8N Altera, EP3C40F484C8N Datasheet - Page 187

• Manufacturer Part Number: EP3C40F484C8N
• Description: IC CYCLONE III FPGA 40K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F484C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 331
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 331
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 2475
• Family Type: Cyclone III
• No. Of I/o's: 331
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2492

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
Altera Corporation
The default read mode of the supported parallel flash memory and all writes to the
parallel flash memory are asynchronous. Both the parallel flash families support a
synchronous read mode, with data supplied on the positive edge of DCLK.
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■
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The serial clock (DCLK) generated by Cyclone III devices controls the entire
configuration cycle and provides timing for the parallel interface. Cyclone III devices
use a 40-Mhz internal oscillator to generate DCLK. The oscillator is the same oscillator
used in the AS configuration scheme. The active DCLK output frequency is listed in
Table 9–8 on page
Multi-Device AP Configuration
You can cascade multiple Cyclone III devices using the chip-enable (nCE) and chip-
enable-out (nCEO) pins. The first device in the chain must have its nCE pin connected
to GND. Connect its nCEO pin to the nCE pin of the next device in the chain. Use an
external 10-kΩ pull-up resistor to pull the nCEO signal high to its V
the internal weak pull-up resistor. When the first device captures all its configuration
data from the bitstream, it drives the nCEO pin low, enabling the next device in the
chain. You can leave the nCEO pin of the last device unconnected or use it as a user
I/O pin after configuration if the last device in the chain is a Cyclone III device. The
nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[15..8], and DATA[7..0] pins of
each device in the chain are connected
page
The first Cyclone III device in the chain, as shown in
Figure 9–10 on page
configuration of the entire chain. Connect its MSEL pins to select the AP configuration
scheme. The remaining Cyclone III devices are used as configuration slaves. Connect
their MSEL pins to select the FPP configuration scheme. Any other Altera device that
supports FPP configuration can also be part of the chain as a configuration slave.
The following are the configurations for the DATA[15..0] bus in a multi-device AP
configuration:
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nRESET is an active-low hard reset
FLASH_nCE is an active-low chip enable
nOE is an active-low output enable for the DATA[15..0] bus and WAIT pin
nAVD is an active-low address valid signal and is used to write addresses into the
flash
nWE is an active-low write enable and is used to write data into the flash
PADD[23..0] bus is the address bus supplied to the flash
DATA[15..0] bus is a bidirectional bus used to supply and read data to and
from the flash, with the flash output controlled by nOE
Byte-wide multi-device AP configuration
Word-wide multi-device AP configuration
9–29).
9–13.
9–29, is the configuration master device and controls the
(Figure 9–9 on page 9–28
Figure 9–9 on page 9–28
Cyclone III Device Handbook, Volume 1
and
CCIO
Figure 9–10 on
level to help
and
9–27