CY7C64013C-SXC Cypress Semiconductor Corp, CY7C64013C-SXC Datasheet

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... USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. GPIO The CY7C64013C features 19 GPIO pins to support USB and other applications. The I/O pins are grouped into three ports (P0[7:0], P1[2:0], P2[6:2], P3[2:0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs ...

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... Memory The CY7C64013C and CY7C64113C have PROM. Power on Reset, Watchdog and Free running Time These parts include power-on reset logic, a Watchdog timer, and a 12-bit free-running timer. The power-on reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address 0x0000 ...

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... PORT 2 P2[4]; STB P2[5]; OE P2[6]; CS High Current P3[2:0] Outputs GPIO Additional PORT 3 P3[7:3] High Current Outputs DAC[0] DAC DAC[2] PORT DAC[7] CY7C64113C only SCLK SDATA Interface 2 *I C-compatible interface enabled by firmware through P2[1:0] or P1[1:0] CY7C64013C CY7C64113C Upstream USB Port Page [+] Feedback ...

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... Sample Schematic .......................................................... 44 Absolute Maximum Ratings .......................................... 45 Electrical Characteristics ............................................... 45 Switching Characteristics .............................................. 46 Ordering Information ...................................................... 48 Ordering Code Definitions ......................................... 48 Package Diagrams .......................................................... 49 Acronyms ........................................................................ 51 Document Conventions ................................................. 51 Units of Measure ....................................................... 51 Document History Page ................................................. 52 Sales, Solutions, and Legal Information ...................... 53 Worldwide Sales and Design Support ....................... 53 Products .................................................................... 53 PSoC Solutions ......................................................... 53 CY7C64013C CY7C64113C Page [+] Feedback ...

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... V REF 4 P3[0] P1[1] 25 P3[2] GND 5 24 P2[2] 23 P3[1] 6 GND D+[ P2[4] D–[ P2[ P2[6] P2[ P0[ P0[0] P0[ P0[2] P0[ P0[4] P0[ P0[6] CY7C64013C CY7C64113C CY7C64113C 48-pin SSOP P1[1] XTALIN 3 46 P1[0] V REF 4 P1[2] P1[3] 45 P1[4] P1[ P1[6] P1[ P3[0] P3[ P3[2] D+[ D–[0] 9 GND 40 P3[ P3[4] GND 11 38 ...

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... I/O register is selected solely by the contents of X. All undefined registers are reserved important not to write to reserved registers as this may cause an undefined operation or increased current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written with ‘0.’ CY7C64013C CY7C64113C Description Page [+] Feedback ...

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... Interrupt Polarity for each DAC Pin W Input Sink Current Control for each DAC Pin Reserved R/W USB Address A, Endpoint 3 Counter R/W USB Address A, Endpoint 3 Configuration R/W USB Address A, Endpoint 4 Counter R/W USB Address A, Endpoint 4 Configuration Reserved Reserved Reserved Reserved Reserved CY7C64013C CY7C64113C Page ...

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... Register Name I/O Address Reserved 0x4D Reserved 0x4E Reserved 0x4F Reserved 0x50 Reserved 0x51 Processor Status & Control 0xFF Document Number: 38-08001 Rev. *D Read/Write Function Reserved Reserved Reserved Reserved Reserved R/W Microprocessor Status and Control Register CY7C64013C CY7C64113C Page 23 Page [+] Feedback ...

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... AND [expr],A 5 AND [X+expr],A 7 XOR [expr],A 8 XOR [X+expr],A 4 IOWX [X+expr] 5 CPL 6 ASL 4 ASR 5 RLC RRC 4 RET RETI JNC 10 JACC 5 INDEX 5 CY7C64013C CY7C64113C operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 address ...

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... RETI instruction. Only the program 27). counter is restored during a RET instruction. The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up. CY7C64013C CY7C64113C Page [+] Feedback ...

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... USB address A endpoint 3 interrupt vector 0x0010 USB address A endpoint 4 interrupt vector 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 2 0x0018 I C interrupt vector 0x001A Program Memory begins here 0x1FDF 8 KB (-32) PROM ends here (CY7C64013C, CY7C64113C) CY7C64013C CY7C64113C Page [+] Feedback ...

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... Address 0x00 Program Stack Growth user selected Data Stack Growth User variables USB FIFO space for five endpoints 0xFF for a description of DSP. Table 34 on page 32. CY7C64013C CY7C64113C [2] Page [+] Feedback ...

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... Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register Address Modes The CY7C64013C and CY7C64113C microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. Data (Immediate) “Data” address mode refers to a data operand that is actually a constant encoded in the instruction ...

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... GPIO interrupt logic and the USB receiver. The clock oscillator and PLL, as well as the free-running and Watchdog timers, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle bus activity at a USB upstream or downstream port CY7C64013C CY7C64113C has risen CC to stabilize at a valid operating voltage ...

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... The data for each GPIO port is accessible through the data registers. Port data registers are shown in on reset P0.5 P0.4 P0.3 R/W R/W R CY7C64013C CY7C64113C CC Q2 GPIO PIN *Port 0,1,2: Low I sink Port 3: High I sink Table 4 through Table 7, and are set to 1 ADDRESS 0x00 2 ...

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... Therefore unused port bit is programmed in open-drain mode, it must be written with a ‘0.’ Notice that the CY7C64013C part always requires that the data bits P1[7:3], P2[7,1,0], and P3[7:3] be written with a ‘0.’ In normal non-HAPI mode, reads from a GPIO port always return the present state of the voltage at the pin, independent of the settings in the Port Data Registers ...

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... All GPIO pins share a common interrupt, as discussed in GPIO/HAPI Interrupt on page P1.3 Intr Enabl CY7C64013C CY7C64113C Interrupt Polarity 0 Disabled 1 – (Falling Edge) 0 Disabled 1 Disabled 0 Disabled 1 – (Falling Edge) 0 Disabled 1 + (Rising Edge) Hardware Assisted Parallel Interface 24) is enabled the GPIO interrupts are blocked, 29 ...

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... I/O pin HIGH through an integrated 14-k resistor. When a ‘0’ is written to a DAC I/O pin, the Isink DAC is enabled and the pull-up resistor is disabled. This causes the I current to drive the output LOW. of the DAC port pin. CY7C64013C CY7C64113C ADDRESS 0x06 2 1 ...

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... The first Isink register (0x38) controls the current for DAC[0], the second (0x39) for DAC[1], and so on until the Isink register at 0x3F controls the current to DAC[7 Reserved Reserved Isink[ CY7C64013C CY7C64113C DAC I/O Pin Table 14) should normally be loaded ADDRESS 0x30 DAC[2] DAC[1] DAC[0] ...

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... The effect of this logic is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time Timer Bit 5 Timer Bit 4 Timer Bit CY7C64013C CY7C64113C 29. ADDRESS 0x31 Enable Bit 2 Enable Bit 1 Enable Bit ...

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... HAPI operation is enabled whenever either HAPI Port Width Bit (Bit non-zero. This affects GPIO operation as described 24. in Hardware Assisted Parallel Interface (HAPI) on page 2 I C-compatible blocks must be separately enabled as described in I2C-compatible Controller on page CY7C64013C CY7C64113C ADDRESS 0x25 Timer Bit 10 Timer Bit 9 Timer Bit 8 R ...

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... R/W R Xmit Mode ACK Addr R/W R/W R Table 26 on page 24, with a more detailed description following. CY7C64013C CY7C64113C Position P2[1:0], 0:SCL, 1:SDA P1[1:0], 0:SCL, 1:SDA P2[1:0], 0:SCL, 1:SDA 2 C Status and Control 2 C interrupt, as all 2 C SDA data is connected to bit 1 of GPIO port ...

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... I C interrupt, the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware during the restart sequence. CY7C64013C CY7C64113C 2 C GPIO pins 2 C Stop bit detected (unless firmware did not 2 C address packet. The Xmit Mode bit state is 2 C-compatible bus ...

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... The Latch Empty bit reads the opposite state from the external LatEmptyPin on pin P2[2]. If the LEMPTY Polarity bit is 0, LatEmptyPin is active HIGH, and the Latch Empty bit is active LOW. CY7C64013C CY7C64113C (Table 20 on page 21), bits 1 15). Figure 13 on page ...

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... During a Watchdog Reset, the Processor Status and Control 01XX0001b, which indicates a Watchdog Reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). The Watchdog Reset does not effect the state of the POR and the Bus Reset Interrupt bits. CY7C64013C CY7C64113C ADDRESS 0xFF ...

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... GPIO Configuration Port on page 16 Interrupt Enable Ports on page 2 Bit Interrupt Enable 1= Enable Interrupt on I2C related activity Disable I2C related activity interrupt. 2 (Refer to I Bit 7 : Reserved CY7C64013C CY7C64113C ADDRESS 0X20 1.024-ms 128-s Interrupt USB Bus RST Interrupt Enable Enable Interrupt Enable ...

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... Control Register). Interrupt Vectors The Interrupt Vectors supported by the USB Controller are listed in Table 30 on page Bus Reset interrupt) has the highest priority, and the highest-numbered interrupt (I Table 27 on page 25). CY7C64013C CY7C64113C ADDRESS 0X21 EPA2 Interrupt EPA1 Interrupt EPA0 Interrupt Enable ...

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... Hub IRQ Interrupt DAC CLR DAC IRQ Acknowledge GPIO CLR GPIO IRQ CLR IRQ Interrupt Priority Encoder instruction is two bytes long, the interrupt vectors occupy two bytes. CY7C64013C CY7C64113C IRQ Sense IRQ Int Enable Sense Controlled by DI, EI, and RETI Instructions Page [+] Feedback ...

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... The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. CY7C64013C CY7C64113C Function Reserved DAC interrupt ...

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... USB Overview The USB hardware consists of the logic for a full-speed USB Port. The full-speed serial interface engine (SIE) interfaces the microcontroller to the USB bus. An external series resistor (R must be placed in series with the D+ and D– lines, as close to CY7C64013C CY7C64113C IRQout Interrupt Q Priority ...

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... Force SE0; D+[0] LOW, D–[0] LOW 100 Force D+[0] LOW, D–[0] LOW 101 Force D+[0] HiZ, D–[0] LOW 110 Force D+[0] LOW, D–[0] HiZ 111 Force D+[0] HiZ, D–[0] HiZ CY7C64013C CY7C64113C Table 31. All bits in the register are ADDRESS 0x1F Control Action ...

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... USB Control Endpoint Mode Register All USB devices are required to have a Control Endpoint 0 (EPA0) that is used to initialize and control each USB address. Endpoint 0 provides access to the device configuration information and allows generic USB status and control accesses. CY7C64013C CY7C64113C for a detailed Table 33 shows the format ...

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... Table 36 Reserved ACK Mode Bit 3 R/W R/W R These sets the mode which control how the control end- point responds to traffic. The mode bit encoding is shown in Table 38 CY7C64013C CY7C64113C Table 35. ADDRESSES 0x12 Mode Bit 2 Mode Bit 1 Mode Bit 0 R/W R/W R Table 34 for the appropriate endpoint zero ...

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... For details on what conditions are required to generate an endpoint interrupt, refer to 4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode register which was locked earlier. CY7C64013C CY7C64113C ADDRESSES 0x11, 0x13, 0x15, 0x41, 0x43 2 ...

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... Device To Host NAK/STALL Data Packet UPDATE Host To Device Data 1/0 Data Packet UPDATE SETUP Host To Device Data 1/0 Data Packet UPDATE only if FIFO is written CY7C64013C CY7C64113C Hand Shake Packet UPDATE Device To Host E S ACK, Y NAK, N STAL C Hand Shake Packet Page [+] Feedback ...

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... USB transactions. For example, if the Mode Bits [3:0] are set to '1111' which is ACK IN-Status OUT mode, the SIE will change the endpoint Mode Bits [3:0] to NAK IN-Status OUT mode (1110) after ACK’ing a valid status stage OUT token. CY7C64013C CY7C64113C Comments Page ...

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... USB request). This read will of course unlock the register. So care must be taken not to overwrite the register elsewhere. CY7C64013C CY7C64113C Interrupt ACK 3 ...

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... updates updates updates updates 0 updates CY7C64013C CY7C64113C ACK Mode Bits Response Intr ACK yes UC NoChange ignore yes UC NoChange ignore yes ACK Mode Bits Response Intr UC NoChange ignore no UC NoChange NAK yes UC NoChange NAK yes UC NoChange ignore no UC NoChange ignore no ...

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... UC 1 updates 1 updates Changes made by SIE to Internal Registers and Mode Bits DTOG DVAL COUNT Setup In Out CY7C64013C CY7C64113C Stall yes UC NoChange ignore no UC NoChange ignore no 1 NoChange TX 0 yes ACK Mode Bits Response Intr 1 NoChange ACK yes Stall yes Stall yes ...

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... Changes made by SIE to Internal Registers and Mode Bits DTOG DVAL COUNT Setup In Out CY7C64013C CY7C64113C ACK yes UC NoChange ignore yes UC NoChange ignore yes UC NoChange ignore no [3] (STALL = 0) UC NoChange Stall no [3] (STALL = 1) UC NoChange NAK yes UC NoChange ignore no UC NoChange ignore no UC NoChange ignore no 1 NoChange RX yes UC ...

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... Data Valid Byte Byte Byte Byte Count Count Count Count Bit 5 Bit 4 Bit 3 Bit ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 CY7C64013C CY7C64113C Bit 1 Bit 0 Read/Write/Both/- Default/Reset P0.1 P0.0 bbbbbbbb 11111111 P1.1 P1.0 bbbbbbbb 11111111 P2.1 P2.0 bbbbbbbb 11111111 P3 ...

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... Data Valid Byte Byte Byte Byte Count Count Count Count Bit 5 Bit 4 Bit 3 Bit ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 CY7C64013C CY7C64113C Bit 1 Bit 0 Read/Write/Both/- Default/Reset Control Control bbrrbbbb -0xx0000 Bit 1 Bit 0 128-s USB Bus -bbbbbbb -0000000 Interrupt ...

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... Document Number: 38-08001 Rev. *D Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Watchdog USB Bus Power-On Suspend Interrupt Reset Reset Reset Enable Interrupt Sense W: Write R: Read CY7C64013C CY7C64113C Bit 1 Bit 0 Read/Write/Both/- Default/Reset Reserved 00000000 Reserved 00000000 Reserved 00000000 Reserved 00000000 Reserved --000000 Reserved 00000000 ...

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... Vbus D– D+ GND SHELL Optional Document Number: 38-08001 Rev. *D 3.3V Regulator Vref OUT IN 2.2 F 2.2 F Vref 0V 1. UUP .01 F Vbus 22x2(R ) ext 0V D0– D0+ 4.7 nF 250VAC XTALO 10M XTALI 6.000 MHz GND 0V GND Vpp 0V CY7C64013C CY7C64113C .01 F 0V Page [+] Feedback ...

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... CC 15 k ±5% to Gnd 1.5 k ± REF Including R Resistor ext All ports, LOW to HIGH edge All ports, HIGH to LOW edge 1.9 mA (all ports 0,1,2, below approximately 2 CY7C64013C CY7C64113C Min Max Unit 3.15 3.45 V –0.4 0.4 V – – 50 µA – – ...

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... out [ 2 out [ 2.0 V out out [8] DAC Port Description Clock Source [ DAC Interface [10, 11] [11] [10, 11] [11] [11] [10, 11] Timer Signals CY7C64013C CY7C64113C Min Max Unit 8.0 24.0 k 0.1 0.3 mA 0.5 1.5 mA 1.6 4 1.6 4.8 mA – 0.6 LSB Min Max Unit 6 ± ...

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... DATA (output) STB (P2.4, input) DReadyPin (P2.3, output) (Shown for DRDY Polarity=0) Internal Write Internal Addr Port0 Document Number: 38-08001 Rev. *D Figure 10. Clock Timing t CYC Figure 11. USB Data Signal Timing 90% 90% 10 D[23:0] t OED t OEDR (Ready) CY7C64013C CY7C64113C 10% Int t OEZ Page [+] Feedback ...

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... Interrupt Generated CS (P2.6, input) STB (P2.4, input) DATA (input) OE (P2.5, input) LEmptyPin (P2.2, output) (Shown for LEMPTY Polarity=0) Internal Read Internal Addr Ordering Information Ordering Code PROM Size CY7C64013C-SXC 8 KB CY7C64013C-SXCT 8 KB Ordering Code Definitions CY 7C64013C - Document Number: 38-08001 Rev STBZ ...

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... Package Diagrams Document Number: 38-08001 Rev. *D Figure 14. 48-pin SSOP Figure 15. 28-pin (300 MIL) PDIP CY7C64013C CY7C64113C 51-85061 *D 51-85014 *E Page [+] Feedback ...

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... Figure 16. 28-pin SOIC (.713 × .300 × .0932 INCHES) Document Number: 38-08001 Rev. *D CY7C64013C CY7C64113C 51-85026 *F Page [+] Feedback ...

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... V Volts µA micro Amperes mA milli Amperes cm centi meter mm milli meter kHz kilo Hertz MHz Mega Hertz pF pico Farad °C degree Celcius % percent mW milli Watts W Watts CY7C64013C CY7C64113C Page [+] Feedback ...

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... Document History Page Document Title: CY7C64013C, CY7C64113C Full-Speed USB (12-Mbps) Function Document Number: 38-08001 Orig. of REV. ECN NO. Issue Date Change ** 109962 12/16/01 *A 129715 02/05/04 *B 429099 See ECN *C 2897159 03/22/10 *D 3190495 03/08/2011 Document Number: 38-08001 Rev. *D Description of Change SZV Change from Spec number: 38-00626 to 38-08001 ...

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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-08001 Rev. *D All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised March 8, 2011 CY7C64013C CY7C64113C PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...