CY7C64013C-SXC Cypress Semiconductor Corp, CY7C64013C-SXC Datasheet - Page 37

• Manufacturer Part Number: CY7C64013C-SXC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013C-SXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 19
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Package: 28SOIC
• Device Core: M8C
• Family Name: enCoRe II
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1847

The firmware needs to update the mode for the SIE to respond
appropriately. See
modes will be changed by the SIE. A disabled endpoint will
remain disabled until changed by firmware, and all endpoints
reset to the disabled mode (0000). Firmware normally enables
the endpoint mode after a SetConfiguration request.
Any SETUP packet to an enabled endpoint with mode set to
accept SETUPs will be changed by the SIE to 0001 (NAKing INs
and OUTs). Any mode set to accept a SETUP will send an ACK
handshake to a valid SETUP token.
The control endpoint has three status bits for identifying the
token type received (SETUP, IN, or OUT), but the endpoint must
The response of the SIE can be summarized as follows:
Document Number: 38-08001 Rev. *D
1. The SIE will only respond to valid transactions, and will ignore
2. The SIE will generate an interrupt when a valid transaction is
3. An incoming Data packet is valid if the count is < Endpoint
4. An IN will be ignored by an OUT configured endpoint and visa
5. The IN and OUT PID status is updated at the end of a
6. The SETUP PID status is updated at the beginning of the Data
7. The entire Endpoint 0 mode register and the Count register
3
Endpoint Mode
encoding
Legend:
non-valid ones.
completed or when the FIFO is corrupted. FIFO corruption
occurs during an OUT or SETUP transaction to a valid internal
address, that ends with a non-valid CRC.
Size + 2 (includes CRC) and passes all error checking;
versa.
transaction.
packet phase.
are locked to CPU writes at the end of any transaction to that
2
1
0
Received Token
(SETUP/IN/OUT)
Token
TX : transmit
RX : receive
x: don’t care
Table 34 on page 32
count
The number of received bytes
available for Control endpoint only
Incoming Packets
Properties of
buffer
The quality status of the DMA buffer
UC : unchanged
TX0 :Transmit 0 length packet
for more details on what
dval
The validity of the received data
Changes to the Internal Register made by the SIE on receiving an incoming packet
DTOG
Data0/1 (bit7 Figure 17-4)
DVAL
Data Valid (bit 6, Figure 17-4)
COUNT
Byte Count (bits 0..5, Figure 17-4)
be placed in the correct mode to function as such. Non-Control
endpoints should not be placed into modes that accept SETUPs.
Note that most modes that control transactions involving an
ending ACK, are changed by the SIE to a corresponding mode
which NAKs subsequent packets following the ACK. Exceptions
are modes 1010 and 1110.
Note: The SIE offers an “Ack out–Status in” mode and not an
“Ack out–Nak in” mode. Therefore, if following the status stage
of a Control Write transfer a USB host were to immediately start
the next transfer, the new Setup packet could override the data
payload of the data stage of the previous Control Write.
endpoint in which an ACK is transferred. These registers are
only unlocked by a CPU read of the register, which should be
done by the firmware only after the transaction is complete.
This represents about a 1- µs window in which the CPU is
locked from register writes to these USB registers. Normally
the firmware should perform a register read at the beginning
of the Endpoint ISRs to unlock and get the mode register
information. The interlock on the Mode and Count registers
ensures that the firmware recognizes the changes that the
SIE might have made during the previous transaction. Note
that the setup bit of the mode register is NOT locked. This
means that before writing to the mode register, firmware must
first read the register to make sure that the setup bit is not set
(which indicates a setup was received, while processing the
current USB request). This read will of course unlock the
register. So care must be taken not to overwrite the register
elsewhere.
from the host
Setup
(Bit[7..5], Figure 17-2)
PID Status Bits
In
Out
ACK
Acknowledge phase completed
3
2 1 0 Response
Changed by the SIE
Endpoint Mode bits
CY7C64013C
CY7C64113C
SIE’s Response
to the Host
Page 37 of 53
Interrupt
Int
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