CY7C64013C-SXC Cypress Semiconductor Corp, CY7C64013C-SXC Datasheet - Page 28

• Manufacturer Part Number: CY7C64013C-SXC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013C-SXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 19
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Package: 28SOIC
• Device Core: M8C
• Family Name: enCoRe II
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1847

Although Reset is not an interrupt, the first instruction executed
after a reset is at PROM address 0x0000h—which corresponds
to the first entry in the Interrupt Vector Table. Because the JMP
Document Number: 38-08001 Rev. *D
AddrA ENP2 Int
USB Reset Int
I
2
C Int
1
1
1
CLK
D
D
CLK
CLK
D
CLR
CLR
CLR
Q
Q
Q
(Reg 0x21)
Enable [2]
(Reg 0x20)
(Reg 0x20)
Enable [0]
Enable [6]
Figure 7. Interrupt Controller Function Diagram
USB Reset IRQ
AddrA EP0 IRQ
AddrA EP1 CLR
AddrA EP1 IRQ
AddrA EP2 CLR
AddrA EP2 IRQ
AddrB EP0 IRQ
AddrB EP1 IRQ
DAC IRQ
128-s CLR
128-s IRQ
1-ms CLR
1-ms IRQ
AddrA EP0 CLR
AddrB EP0 CLR
AddrB EP1 CLR
Hub CLR
Hub IRQ
DAC CLR
GPIO CLR
GPIO IRQ
I
USB Reset Clear Interrupt
I
2
2
Interrupt Priority Encoder
C CLR
C IRQ
instruction is two bytes long, the interrupt vectors occupy two
bytes.
IRQout
Vector
Acknowledge
To CPU
CPU
Interrupt
Interrupt
Enable
Global
CLR
Bit
Controlled by DI, EI, and
RETI Instructions
CY7C64013C
CY7C64113C
IRQ Sense
Int Enable
Sense
Page 28 of 53
IRQ
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