CY7C64013C-SXC Cypress Semiconductor Corp, CY7C64013C-SXC Datasheet - Page 24

• Manufacturer Part Number: CY7C64013C-SXC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013C-SXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 19
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Package: 28SOIC
• Device Core: M8C
• Family Name: enCoRe II
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1847

Bit 1 : Receive Stop
Bit 0 : I
Table 26. Port 2 Pin and HAPI Configuration Bit Definitions
HAPI Read by External Device from CY7C64x13C:
In this case (see
ports. If 16-bit or 24-bit transfers are being made, Port 0 should
be written last, since writes to Port 0 asserts the Data Ready bit
and the DReady Pin to signal the external device that data is
available.
The external device then drives the OE and CS pins active
(LOW), which causes the HAPI data to be output on the port pins.
When OE is returned HIGH (inactive), the HAPI/GPIO interrupt
is generated. At that point, firmware can reload the HAPI latches
for the next output, again writing Port 0 last.
The Data Ready bit reads the opposite state from the external
DReadyPin on pin P2[3]. If the DRDY Polarity bit is 0, DReadyPin
is active HIGH, and the Data Ready bit is active LOW.
Document Number: 38-08001 Rev. *D
P2[2]
P2[3]
P2[4]
P2[5]
P2[6]
Bit
2
3
4
5
Pin
This bit is set when the slave is in receive mode and
detects a stop bit on the bus. The Receive Stop bit is not
set if the firmware terminates the I
acknowledging the previous byte transmitted on the
I
the Continue bit and clears the ACK bit.
Set this bit to override GPIO definition with I
function on the two I
cleared, these pins are free to function as GPIOs. In
I
mode, independent of the GPIO configuration setting.
2
2
2
C-compatible bus, e.g. in receive mode if firmware sets
C-compatible mode, the two pins operate in open drain
C Enable
LatEmptyPin
DReadyPin
STB
OE
CS
Name
Data Ready
Latch Empty
DRDY Polarity
LEMPTY Polarity
Figure
Name
12), firmware writes data to the GPIO
2
C-compatible pins. When this bit is
Out
Out
In
In
In
R/W
R
R
R/W
R/W
Direction
2
C transaction by not
Ready for more input data from external interface.
Output data ready for external interface.
Strobe signal for latching incoming data.
Output Enable, causes chip to output data.
Chip Select (Gates STB and OE).
Description (HAPI/I
Asserted after firmware writes data to Port 0, until OE driven LOW.
Asserted after firmware reads data from Port 0, until STB driven LOW.
Determines polarity of Data Ready bit and DReadyPin:
If 0, Data Ready is active LOW, DReadyPin is active HIGH.
If 1, Data Ready is active HIGH, DReadyPin is active LOW.
Determines polarity of Latch Empty bit and LatEmptyPin:
If 0, Latch Empty is active LOW, LatEmptyPin is active HIGH.
If 1, Latch Empty is active HIGH, LatEmptyPin is active LOW.
2
C-compatible
Hardware Assisted Parallel Interface (HAPI)
The CY7C64x13C processor provides a hardware assisted
parallel interface for bus widths of 8, 16, or 24 bits, to
accommodate data transfer with an external microcontroller or
similar device. Control bits for selecting the byte width are in the
HAPI/I
and 0.
Signals are provided on Port 2 to control the HAPI interface.
Table 26
HAPI/I
GPIO setting in the GPIO Configuration Register (0x08) to be
overridden. The Port 2 output pins are in CMOS output mode and
Port 2 input pins are in input mode (open drain mode with Q3
OFF in
2
HAPI Write by External Device to CY7C64x13C:
In this case (see
drives the STB and CS pins active (LOW) when it drives new
data onto the port pins. When this happens, the internal latches
become full, which causes the Latch Empty bit to be deasserted.
When STB is returned HIGH (inactive), the HAPI/GPIO interrupt
is generated. Firmware then reads the parallel ports to empty the
HAPI latches. If 16-bit or 24-bit transfers are being made, Port 0
should be read last because reads from Port 0 assert the Latch
Empty bit and the LatEmptyPin to signal the external device for
more data.
The Latch Empty bit reads the opposite state from the external
LatEmptyPin on pin P2[2]. If the LEMPTY Polarity bit is 0,
LatEmptyPin is active HIGH, and the Latch Empty bit is active
LOW.
C Configuration Register)
Description (Port 2 Pin)
2
2
C Configuration Register
C Configuration Register. Enabling HAPI causes the
Figure 3 on page
describes these signals and the HAPI control bits in the
Figure 13 on page
15).
(Table 20 on page
48), the external device
CY7C64013C
CY7C64113C
Page 24 of 53
21), bits 1
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