CY7C64013C-SXC Cypress Semiconductor Corp, CY7C64013C-SXC Datasheet - Page 15

• Manufacturer Part Number: CY7C64013C-SXC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013C-SXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 19
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Package: 28SOIC
• Device Core: M8C
• Family Name: enCoRe II
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1847

wakes the part out of suspend. The Run bit in the Processor
Status and Control Register must be set to resume a part out of
suspend.
The clock oscillator restarts immediately after exiting suspend
mode. The microcontroller returns to a fully functional state 1 ms
after the oscillator is stable. The microcontroller executes the
instruction following the I/O write that placed the device into
suspend mode before servicing any interrupt requests.
Typical code for entering suspend is shown below:
General-Purpose I/O (GPIO) Ports
There are up to 32 GPIO pins (P0[7:0], P1[7:0], P2[7:0], and
P3[7:0]) for the hardware interface. The number of GPIO pins
changes based on the package type of the chip. Each port can
be configured as inputs with internal pull-ups, open drain outputs,
or traditional CMOS outputs. Port 3 offers a higher current drive,
Table 4. Port 0 Data
Document Number: 38-08001 Rev. *D
Port 0 Data
Bit #
Bit Name
Read/Write
Reset
...
...
mov a, 09h
iowr FFh
nop
...
; All GPIO set to low-power state (no floating pins)
; Enable GPIO interrupts if desired for wake-up
; Set suspend and run bits
; Write to Status and Control Register - Enter suspend, wait for USB activity (or GPIO Interrupt)
; This executes before any ISR
; Remaining code for exiting suspend routine
P0.7
R/W
7
1
(Latch is Transparent
except in HAPI mode)
Interrupt
Controller
Interrupt
Enable
Port Write
OE
Reg_Bit
Port Read
Internal
Data Bus
STRB
P0.6
R/W
6
1
GPIO
CFG
Figure 3. Block Diagram of a GPIO Pin
P0.5
R/W
5
1
Data
In
Latch
Data
Interrupt
Latch
Data
Out
Latch
P0.4
R/W
4
1
The GPIO interrupt allows the controller to wake-up periodically
and poll system components while maintaining a very low
average power consumption. To achieve the lowest possible
current during suspend mode, all I/O should be held at V
Gnd. This also applies to internal port pins that may not be
bonded in a particular package.
mode
2-bits
with typical current sink capability of 12 mA. The data for each
GPIO port is accessible through the data registers. Port data
registers are shown in
on reset.
P0.3
R/W
3
1
Q3*
Q1
14 k
V
CC
Q2
*Port 0,1,2: Low I
P0.2
R/W
Table 4
Port 3: High I
1
2
through
GPIO
PIN
P0.1
R/W
sink
1
1
Table
sink
CY7C64013C
CY7C64113C
7, and are set to 1
ADDRESS 0x00
Page 15 of 53
P0.0
R/W
0
1
CC
or
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