CY7C64013C-SXC Cypress Semiconductor Corp, CY7C64013C-SXC Datasheet - Page 40

• Manufacturer Part Number: CY7C64013C-SXC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013C-SXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 19
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Package: 28SOIC
• Device Core: M8C
• Family Name: enCoRe II
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1847

Document Number: 38-08001 Rev. *D
Table 39. Details of Modes for Differing Traffic Conditions (see
Normal Out/erroneous In
1
1
1
1
1
NAK Out/erroneous In
1
1
1
1
Isochronous endpoint (Out)
0
0
IN ENDPOINT
Properties of Incoming Packet
Mode Bits
Normal In/erroneous Out
1
1
1
NAK In/erroneous Out
1
1
Isochronous endpoint (In)
0
0
Note:
3. STALL bit is bit 7 of the USB Non-Control Device Endpoint Mode registers. For more information, refer to Sec.
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
Out
Out
Out
In
In
Out
Out
Out
In
Out
In
token
Out
Out
In
Out
In
Out
In
<= 10
> 10
x
x
x
<= 10
> 10
x
x
x
x
count
x
x
x
x
x
x
x
buffer
data
junk
junk
UC
UC
UC
UC
UC
UC
updates updates updates updates updates UC
UC
UC
UC
UC
UC
UC
UC
UC
valid
dval
valid
x
invalid
x
x
x
invalid
x
x
x
x
x
x
x
x
x
UC
DTOG
updates 1
updates updates updates UC
updates 0
UC
UC
UC
UC
UC
UC
Changes made by SIE to Internal Registers and Mode Bits
UC
UC
UC
UC
UC
UC
UC
Table 38
UC
DVAL
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
for the decode legend) (continued)
updates UC
updates UC
UC
UC
UC
UC
UC
UC
UC
COUNT Setup
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
In
UC
UC
1
UC
1
UC
1
UC
UC
UC
UC
UC
1
UC
UC
UC
1
UC
Out
UC
UC
UC
UC
UC
UC
UC
1
UC
UC
UC
UC
UC
UC
UC
UC
1
UC
ACK
UC
UC
1
UC
UC
UC
UC
1 0 0 0 ACK
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
Mode Bits
NoChange
NoChange
1 1 0 0 ACK (back)
NoChange
NoChange
NoChange
NoChange
ignore
NAK
RX
ignore
ignore
(STALL
Stall
(STALL
ignore
ignore
ignore
ignore
Response
ignore
(STALL
stall
(STALL
ignore
NAK
ignore
TX
CY7C64013C
CY7C64113C
[3]
[3]
[3]
[3]
= 0)
= 1)
= 0)
= 1)
Page 40 of 53
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