CY7C64013C-SXC Cypress Semiconductor Corp, CY7C64013C-SXC Datasheet - Page 22

• Manufacturer Part Number: CY7C64013C-SXC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013C-SXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 19
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Package: 28SOIC
• Device Core: M8C
• Family Name: enCoRe II
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1847

Table 21. HAPI Port Configuration
Table 22. I
I
The I
communication with external devices, supporting master, slave,
and multi-master modes of operation. The I
functions by handling the low-level signaling in hardware, and
issuing interrupts as needed to allow firmware to take
appropriate action during transactions. While waiting for
firmware response, the hardware keeps the I
idle if necessary.
The I
microcontroller at the end of each received or transmitted byte,
when a stop bit is detected by the slave when in receive mode,
or when arbitration is lost. Details of the interrupt responses are
given in
The I
Data Register
(Table
Table 23. I
Bits [7..0] : I
Table 24. I
The I
Document Number: 38-08001 Rev. *D
I
2
C-compatible Controller
2
I
Bit #
Bit Name
Read/Write
Reset
I
Control
Bit #
Bit Name
Read/Write
Reset
Port Width (Bits[1:0])
2
2
C Data
C Status and
C-compatible Controller
2
2
Contains the 8 bit data on the I
C Status and Control register bits are defined in
2
C-compatible interface consists of two registers, an I
2
24). The Data Register is implemented as separate read
C-compatible block generates an interrupt to the
C-compatible block provides a versatile two-wire
I
2
I
C Interrupt on page
2
11
10
01
00
2
2
2
C Position (Bit[7])
C Port Configuration
C Data Register
C Status and Control Register
2
C Data
(Table
MSTR Mode
I
2
C Data 7
R/W
R/W
X
0
1
7
X
7
0
23) and an I
24 Bits: P3[7:0], P1[7:0], P0[7:0]
Continue/Busy
30.
16 Bits: P1[7:0], P0[7:0]
I
2
C Data 6
2
No HAPI Interface
R/W
R/W
HAPI Port Width
C Status and Control Register
6
X
6
0
8 Bits: P0[7:0]
2
C Bus
2
C-compatible block
2
Xmit Mode
I
C-compatible bus
2
C Data 5
R/W
R/W
5
X
5
0
Port Width (Bit[1])
Table 26 on page
I
2
1
0
0
2
C Data 4
ACK
C
R/W
R/W
4
X
4
0
and write registers. Generally, the I
Register should only be monitored after the I
bits are valid at that time. Polling this register at other times could
read misleading bit status if a transaction is underway.
The I
port 2, and the I
1 or GPIO port 2. Refer to
on page 21
Configuration Register, which is used to set the locations of the
configurable I
functionality is enabled by setting bit 0 of the I
Register, the two LSB bits ([1:0]) of the corresponding GPIO port
are placed in Open Drain mode, regardless of the settings of the
GPIO Configuration Register.The electrical characteristics of the
I
2. Note that the I
All control of the I
I
2
2
C-compatible interface is the same as that of GPIO ports 1 and
C-compatible block.
24, with a more detailed description following.
2
I
C SCL clock is connected to bit 0 of GPIO port 1 or GPIO
2
C Data 3
Addr
R/W
R/W
X
3
3
0
for the bit definitions and functionality of the HAPI/I
2
C-compatible pins. Once the I
2
OL
C SDA data is connected to bit 1 of GPIO port
2
(max) is 2 mA @ V
Lost/Restart
C clock and data lines is performed by the
I
2
C Data 2
I
I
I
R/W
ARB
R/W
2
2
2
X
C on P2[1:0], 0:SCL, 1:SDA
C on P1[1:0], 0:SCL, 1:SDA
C on P2[1:0], 0:SCL, 1:SDA
2
2
0
I
2
C and HAPI Configuration Register
I
2
C Position
Received Stop
I
2
C Data 1
R/W
R/W
OL
X
1
1
0
2
= 2.0 V for ports 1 and 2.
C Status and Control
CY7C64013C
CY7C64113C
2
2
ADDRESS 0x29
C Status & Control
C interrupt, as all
I
I
2
2
C Enable
2
C Data 0
Page 22 of 53
C-compatible
R/W
R/W
X
0
0
0
2
C
[+] Feedback