CY7C64013C-SXC Cypress Semiconductor Corp, CY7C64013C-SXC Datasheet - Page 20

• Manufacturer Part Number: CY7C64013C-SXC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013C-SXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 19
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Package: 28SOIC
• Device Core: M8C
• Family Name: enCoRe II
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1847

Bit [4..0]: Isink [x] (x= 0..4)
Writing all ‘0’s to the Isink register causes 1/5 of the max current
to flow through the DAC I/O pin. Writing all ‘1’s to the Isink
register provides the maximum current flow through the pin. The
other 14 states of the DAC sink current are evenly spaced
between these two values.
Bit [7..5]: Reserved
Table 16. DAC Port Interrupt Enable
Bit [7..0]: Enable bit x (x= 0..2, 7)
1= Enables interrupts from the corresponding bit position;
0= Disables interrupts from the corresponding bit position
As an additional benefit, the interrupt polarity for each DAC pin
is programmable with the DAC Port Interrupt Polarity register.
Writing a ‘0’ to a bit selects negative polarity (falling edge) that
Table 17. DAC Port Interrupt Polarity
Bit [7..0]: Enable bit x (x= 0..2, 7)
1= Selects positive polarity (rising edge) that causes an interrupt
(if enabled);
0= Selects negative polarity (falling edge) that causes an
interrupt (if enabled)
12-Bit Free-Running Timer
The 12-bit timer provides two interrupts (128-µs and 1.024-ms)
and allows the firmware to directly time events that are up to 4 ms
Table 18. Timer LSB Register
Document Number: 38-08001 Rev. *D
DAC Port
Interrupt
Bit #
Bit Name
Read/Write
Reset
DAC Port
Interrupt
Polarity
Bit #
Bit Name
Read/Write
Reset
Timer LSB
Bit #
Bit Name
Read/Write
Reset
Enable Bit 7
Enable Bit 7
Timer Bit 7
W
W
R
7
0
7
0
7
0
Timer Bit 6
Reserved
Reserved
R
W
W
6
0
6
0
6
0
Timer Bit 5
Reserved
Reserved
R
W
W
5
0
5
0
5
0
Timer Bit 4
Reserved
Reserved
R
W
W
4
0
4
0
4
0
DAC Port Interrupts
A DAC port interrupt can be enabled/disabled for each pin
individually. The DAC Port Interrupt Enable register provides this
feature with an interrupt enable bit for each DAC I/O pin.All of the
DAC Port Interrupt Enable register bits are cleared to ‘0’ during
a reset. All DAC pins share a common interrupt, as explained in
DAC Interrupt on page
causes an interrupt (if enabled) if a falling edge transition occurs
on the corresponding input pin. Writing a ‘1’ to a bit in this register
selects positive polarity (rising edge) that causes an interrupt (if
enabled) if a rising edge transition occurs on the corresponding
input pin. All of the DAC Port Interrupt Polarity register bits are
cleared during a reset.
in duration. The lower 8 bits of the timer can be read directly by
the firmware. Reading the lower 8 bits latches the upper 4 bits
into a temporary register. When the firmware reads the upper
4 bits of the timer, it is accessing the count stored in the
temporary register. The effect of this logic is to ensure a stable
12-bit timer value can be read, even when the two reads are
separated in time.
Timer Bit 3
Reserved
Reserved
R
3
0
W
W
3
0
3
0
Enable Bit 2
Enable Bit 2
Timer Bit 2
R
29.
2
0
W
W
2
0
2
0
Timer Bit 1
Enable Bit 1
Enable Bit 1
R
1
0
W
W
1
0
1
0
CY7C64013C
CY7C64113C
ADDRESS 0x24
ADDRESS 0x31
ADDRESS 0x32
Timer Bit 0
Enable Bit 0
Enable Bit 0
Page 20 of 53
R
0
0
W
W
0
0
0
0
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