MPC8560PX833LB Freescale Semiconductor, MPC8560PX833LB Datasheet - Page 52

• Manufacturer Part Number: MPC8560PX833LB
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8560PX833LB

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

I2C
11.2
Table 41
Figure 16
Figure 37
52
All values refer to V
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Hold time (repeated) START condition (after this period, the
first clock pulse is generated)
Data setup time
Data hold time:
Set-up time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected device
(including hysteresis)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
6. Guaranteed by design.
(reference)(state)
symbolizes I
clock reference (K) going to the high (H) state or setup time. Also, t
the data with respect to the start condition (S) went invalid (X) relative to the t
(L) state or hold time. Also, t
condition (P) reaching the valid state (V) relative to the t
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
the undefined region of the falling edge of SCL.
B
= capacitance of one bus line in pF.
provides the AC timing parameters for the I
I
provides the AC test load for the I
shows the AC timing diagram for the I
2
C AC Electrical Specifications
IH
2
(min) and V
C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
for inputs and t
I2DVKH
Output
Parameter
has only to be met if the device does not stretch the LOW period (t
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
IL
(max) levels (see
I2PVKH
(first two letters of functional block)(reference)(state)(signal)(state)
CBUS compatible masters
Table 41. I
symbolizes I
Figure 36. I
Table
I
2
Z
C bus devices
0
2
= 50 Ω
C AC Electrical Specifications
40).
2
2
C.
C timing (I2) for the time that the data with respect to the stop
2
2
C bus.
C AC Test Load
I2C
2
C interface of the MPC8560.
clock reference (K) going to the high (H) state or setup
Symbol
t
t
t
t
I2SVKH
I2DVKH
t
I2SXKL
t
I2PVKH
t
t
I2KHDX
I2DXKL
I2CH
I2CL
V
V
f
I2C
NH
NL
I2SXKL
6
6
6
6
6
1
R
(first two letters of functional block)(signal)(state)
L
symbolizes I
= 50 Ω
0.1 × OV
0.2 × OV
I2C
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
0
—
0
clock reference (K) going to the low
2
for outputs. For example, t
IHmin
DD
DD
OV
2
C timing (I2) for the time that
DD
of the SCL signal) to bridge
I2CL
/2
) of the SCL signal.
Freescale Semiconductor
0.9
Max
400
—
—
—
—
—
—
—
—
—
—
3
I2DVKH
Unit
kHz
μs
μs
μs
μs
ns
μs
μs
μs
V
V
I2C