MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 218

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
State 1
State 2
State 0
The processor asserts ECS and OCS in SO to indicate the beginning of an
and valid function codes on FC0-FC2. The function codes select the address
space for the operation. SIZ0-SIZ1 become valid in SO to indicate the
disable the data buffers.
One-half clock later in $1, the processor asserts AS, indicating that the
address on the address bus is valid. The processor also asserts DS during
The selected device uses R/W, SIZ0-SIZ1, A0-A1, and CLOUT to place its
data. If the selected data is not to be cached for the current cycle or if the
device cannot supply 32 bits, CIIN must be asserted at the same time as
STERM.
Since CIIN and STERM are synchronous signals, they must meet the syn-
chronous input setup and hold times for all rising edges of the clock while
AS is asserted. If STERM is negated at the beginning of S2, wait states are
external operand cycle. The processor also asserts RMC in SO to identify
a read-modify-write cycle. The processor places a valid address on A0-A31
operand size. The processor drives R/W high for a read cycle and sets
CLOUT to the value of the MMU CI bit in the address translation descriptor
or in the appropriate TTx register. The processor drives DBEN inactive to
$1. In addition, the ECS (and OCS, if asserted) signal is negated during $1.
information on the data bus. Any or all of the byte sections (D24-D31,
D16-D23, D8-D15, and D0-D7) are selected by SIZ0-SIZ1 and A0-A1. Dur-
ing $2, the processor drives DBEN active to enable external data buffers.
In systems that use two-clock synchronous bus cycles, the timing of DBEN
may prevent its use. At the beginning of $2, the processor samples the
level of STERM. If STERM is recognized, the processor latches the incoming
inserted after $2, and STERM is sampled on every rising edge thereafter
until it is recognized. Once STERM is recognized, data is latched on the
next falling edge of the clock (corresponding to the beginning of $3).
MC68030 USER'S MANUAL
7-57
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