MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 274

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8.1.2 Bus Error E x c e p t i o n
MOTOROLA
As described in 7.5.4 Double Bus Fault, if bus error or address error occur
to indicate the halted condition.
A bus error exception occurs when external logic aborts a bus cycle by
during the exception processing sequence for a reset,
occurs. The processor halts, and the STATUS signal is asserted continuously
Execution of the reset instruction does not cause a reset exception, nor does
asserting the BERR input signal. If the aborted bus cycle is a data access, the
signal during the second, third, or fourth access of a burst operation does
BURST MODE FILLING and 7.5.1 Bus Errors for details on the effects of bus
errors during burst operation.
A bus error exception also occurs when the MMU detects that a successful
address translation is not possible. Furthermore, when an ATC miss occurs
and an external bus cycle is required, the MMU must abort the bus cycle,
search the translation tables in memory for the mapping, and then retry the
a problem encountered during the table search (the attempt to access the
appropriate page descriptor in the translation tables for that page), a bus
error exception occurs when the aborted bus cycle is retried.
The problem encountered could be a limit violation, an invalid descriptor, or
the assertion of the BERR signal during a bus cycle used to access the trans-
it affect any internal registers, but it does cause the MC68030 to assert the
RESET signal, resetting all external devices.
processor immediately begins exception processing. If the aborted bus cycle
is an instruction prefetch, the processor may delay taking the exception until
it attempts to use the prefetched information. The assertion of the BERR
not cause a bus error exception, but the burst is aborted. Refer to 6.1.3.2
bus cycle. If a valid translation for the logical address is not available due to
a table search but does not cause a bus error exception unless one of the
specific conditions mentioned above is encountered.
lation tables. A miss in the ATC causes the processor to automatically initiate
MC68030 USER'S MANUAL
a;
double bus fault
8-7
8