MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 587

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Data, Immediate, 2-21
Data Buffer Enable Signal, 5-6, 7-5, 7-31ff
Data Burst Enable Bit, 6-21
Data
Data Strobe Signal, 5-6, 7-5, 7-27ff
Data Transfer and Size Acknowledge Signals, 5-6,
DBE Bit, 6-16
DBEN Signal, 5-6, 7-5, 7-31ff
Debugging Aids, 12-35
Decoding, MMU Status Register, 9-61-9-64
Definition, Task Memory Map, 9-66
Delay, Input, 7-2
Derivation, Table Index, 9-9
Description, General, 1-1
Descriptor,
INDEX-4
Cycle,
Cycles, Data Transfer, 7-30
Transfer
Types, 1-10
Table,
Cache, 1-16, 6-1, 6-6, 11-4, 11-16
Port
Register Direct Mode, 2-9
Registers, 1-6, 2-2
Select, Byte, 7-25
6-11, 6-14, 7-5, 7-6, 7-26ff
Invalid,
Page, Early Termination,
Page,
Root Pointer, 9-23
Bus, 5-4, 7-5, 7-30ff, 12-9
Movement Instructions, 3-4
Bits, Unused, 9-71
Fetch Operation Flowchart, 9-44
Indirect,
Asynchronous Read, 7-31
Breakpoint Acknowledge, 7-74
Burst, 7-59, 12-17
Coprocessor Communication, 7-74
Interrupt Acknowledge, 7-69
Interrupt Acknowledge, Autovector, 7-71
Transfer Mechanism, 7-6
Activity, 12-10
Write Enable Signals, 7-23
Cycles, 7-30
Short Format, 9-26
Short Format, 9-26
Short Format, 9-25
Short Format, 9-26
Long Format, 9-24
Short Format, 9-24
Requirements, Read Cycle, 7-10
Long Format, 9-28
Long Format, 9-28
Long Format, 9-25
Long Format, 9-26
Organization,
7-8
- - D i n
MC68030 USER'S MANUAL
Early Termination, 9-23, 9-70
Early Termination Control, 12-34
ECS Signal, 5-5, 7-4, 7-26ff
ED Bit, 6-22
Effective Address Encoding Summary, 2-22
El Bit, 6-23
Empty/Reset Format Word, 10-22
Enable Data Cache Bit, 6-22
Enable Instruction Cache Bit, 6-23
Encoding,
Entry, Address Translation Cache, 9-17
Errors, Bus, 7-82
EU, 6-16
Example,
Exception,
Descriptors, Translation Table, 9-10, 9-20
DFC, 1-8, 2-4
Differences,
DMA Coprocessor, 10-5
Double Bus Fault, 7-94, 8-7
Doubly-Linked List
DR Bit, 10-36
DS Signal, 5-6, 7-5, 7-27ff
DSACK0 Signal, 5-6, 6-11, 6-14, 7-5, 7-6, 7-26ff,
DSACK1 Signal, 5-6, 6-11, 6-14, 7-5, 7-6, 7-26ff,
Dynamic Allocation, Table, 9-40
Dynamic Bus Sizing, 7-6, 7-19, 7-24
D0-D31 Signals, 5-4, 7-5, 7-30ff
D0-DT, 1-6
Address Offset, 7-9
Size Signal, 7-9
Table Paging, 9-39
Table Sharing, 9-32
Two Task Translation Tree, 9-47
Address Error, 8-8, 10-72
CAS Instruction, 3-25
CAS2 Instruction, 3-25
Contiguous Memory, 9-35
Doubly-Linked List
Function Code Lookup, 9-46
Indirection, 9-36
Linked List
Protection, Translation Tree, 9-50
System Paging Implementation, 9-72
Breakpoint Instruction, 8-22
cpTRAPcc Instruction, 10-69
MC68020 Hardware, 12-3
MC68020 Software, 12-4
MMU, 9-51
Deletion Example, 3-30
Insertion Example, 3-29
Bus Error, 8-7, 10-72
Deletion, 3-27
Insertion, 3-26
Deletion, 3-30
Insertion, 3-29
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