MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 331

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9
9-30
The table search procedure uses physical addresses to access the translation
tables. The read-modify-write (RMC) signal is asserted on the first bus cycle
The first bus cycle of the search uses the table address field of the appropriate
the function code or the set of logical address bits defined by the TIA field
The first access obtains a descriptor. If the descriptor is a table descriptor,
the MC68030 again accesses memory. The next access uses the table address
tion code, the second access uses the bits selected by the TIA field of the TC
Additional accesses are performed, using the logical address bits specified
fields.
of the search and remains asserted throughout, ensuring that the entire table
search completes without interruption.
address are supplied by the logical address. The table is indexed by either
of the TC register. The FCL field of the TC register determines whether or
not the function code is used. In either case, the descriptor-type field of the
root pointer selects the scale factor (or multiplier) for the index.
in the descriptor as the base address for the next .table. The low-order bits
of the address are supplied by the logical address. The table is indexed by
a set of bits from the logical address using a scale factor determined by the
descriptor type code in the descriptor. If the first table access used the func-
register. Otherwise, the second access uses the bits selected by the TIB field.
in TIB, TIC, or TID in order, until an access obtains a page descriptor or an
invalid descriptor or until a limit violation occurs. At this point, whether or
over. The page descriptor contains the physical address and other infor-
root pointer as the base address of the first table. The low-order bits of the
not all levels of the address table have been accessed, the table search is
mation needed for the ATC entry; the MC68030 creates the ATC entry and
retries the original bus access.
Figure 9-20 shows a table search using the function code and all four TIx
Table 9-2. Translation Tree Selection
FC2
0
0
1
1
MC68030 USER'S MANUAL
SRE
0
0
1
1
Translation Table
Root Pointer
CRP
CRP
CRP
SRP
MOTOROLA