MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 71

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

2
2,26
extended further. Since displacements can be 32 bits wide, they
dresses. This allows the general register indirect form to be (bd,Rn) or
dress can be directly indexed by one or two registers (refer to Figure 2-6).
calculation (the actual value in the index register remains unchanged). This
to the effective address calculation time. However, when combined with the
tures can be addressed absolutely and then subscripted, (bd,Rn*scale), for
For both the MC68020 and the MC68030, the register indirect modes can be
absolute addresses or the results of expressions that contain absolute ad-
(bd,An,Rn) when the base register is not suppressed. Thus, an absolute ad-
Scaling provides an optional shifting of the value in an index register to the
left by zero, one, two, or three bits before using it in the effective address
is equivalent to multiplying the register by one, two, four, or eight for direct
subscripting into an array of elements of corresponding size using an arith-
metic value residing in any of the 16 general registers. Scaling does not add
appropriate derived modes, it produces additional capabilities. Arrayed struc-
example. Optionally, an address register that contains a dynamic displace-
variation that can be derived is (An,Rn*scale). In the first case, the array
address is the sum of the contents of a register and a displacement, as shown
ment can be included in the address calculation (bd,An,Rn*scale). Another
in Figure 2-7. In the second example, An contains the address of an array
and Rn contains a subscript.
Figure 2-6. Using Absolute Address with Indexes
bd
MC68030 USER'S MANUAL
SYNTAX: (bd,An.Rn)
An
Rn
I
c a n
MOTOROLA
represent