MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 239

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-78
for both of them is met for the same falling edge of the processor clock.
The acceptable bus cycle terminations for asynchronous cycles are sum-
Table 7-8):
To properly control termination of a bus cycle for a retry or a bus error
condition, DSACKx, BERR, and HALT can be asserted and negated with the
asserted simultaneously, the required setup time (#47A) and hold time (#47B)
(Refer to MC68030EC/D,
external circuitry that provides these signals.
marized in relation to DSACKx assertion as follows (case numbers refer to
rising edge of the MC68030 clock. This assures that when two signals are
ments.) This or some equivalent precaution should be designed into the
Normal Termination:
Halt Termination:
Bus Error Termination:
Retry Termination:
3) or after DSACKx (case 4), and HALT remains negated; BERR is
DSACKx is asserted; BERR and HALT remain negated (case 1).
negated at the same time or after DSACKx.
same time or after DSACKx; HALT may be negated at the same time
or after BERR.
HALT is asserted at same time or before DSACKx, and BERR remains
negated (case 2).
BERR is asserted in lieu of, at the same time, or before DSACKx (case
HALT and BERR are asserted in lieu of, at the same time, or before
DSACKx (case 5) or after DSACKx (case 6); BERR is negated at the
MC68030 USER'S MANUAL
MC68030 Electrical Specifications
for timing require-
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