LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 37

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.3.5.3.2
3.3.5.3.3
3.3.5.3.4
EEDIO (OUTPUT)
EEDIO (INPUT)
EECLK
EECS
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the
contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit
is set if the EEPROM does not respond within 30ms.
Table 3.4, "Required EECLK
each EEPROM operation.
HOST INITIATED MAC ADDRESS, SSID, SSVID RELOAD
The Host can initiate a reload of the MAC address, SSID, and SSVID from the EEPROM by issuing
the RELOAD command via the E2P command (E2P_CMD) register. If the first byte read from the
EEPROM is not A5h, it is assumed that the EEPROM is not present, or not programmed, and the
RELOAD operation will fail. The “EEPROM Loaded” bit indicates a successful reload of the MAC
address, SSID, and SSVID.
EEPROM COMMAND AND DATA REGISTERS
Refer to
"EEPROM Data Register (E2P_DATA)," on page 102
Supported EEPROM operations are described in these sections.
EEPROM TIMING
Refer to
OPERATION
ERASE
WRITE
EWDS
EWEN
READ
WRAL
ERAL
Section 4.2.11, "EEPROM Command Register (E2P_CMD)," on page 99
Section 5.8, "EEPROM Timing," on page 165
1
0
0
Figure 3.14 EEPROM WRAL Cycle
Table 3.4 Required EECLK Cycles
0
Cycles", shown below, shows the number of EECLK cycles required for
DATASHEET
1
37
REQUIRED EECLK CYCLES
D7
for detailed EEPROM timing specifications.
for a detailed description of these registers.
10
10
10
10
18
18
18
D0
t
CSL
Revision 1.4 (12-17-08)
and
Section 4.2.12,