LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 62

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Revision 1.4 (12-17-08)
DST
0
The RXCOE supports a maximum of two VLAN tags. If there are more than two VLAN tags, the VLAN
protocol identifier for the third tag is treated as an Ethernet type field. The checksum calculation will
begin immediately after the type field.
The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame it
calculates the 16-bit checksum. The RXCOE passes the Ethernet frame to the DMAC with the
checksum appended to the end of the frame. The RXCOE inserts the checksum immediately after the
last byte of the Ethernet frame. The frame length field (FL) of receive descriptor 0 (RDES0) indicates
that the frame size is increased by two bytes to accommodate the checksum.
Setting the RX_COE_EN bit in the
RXCOE, while the RX_COE_MODE bit selects the operating mode. When the RXCOE is disabled, the
received data is simply passed through the RXCOE unmodified.
Note: Software applications must stop the receiver and flush the RX data path before changing the
Note: When the RXCOE is enabled, automatic pad stripping must be disabled (PADSTR bit of the
DST
0
1
SRC
1
Figure 3.24 Ethernet Frame with multiple VLAN Tags and SNAP Header
{DSAP, SSAP, CTRL,
SRC
2
state of the RX_COE_EN or RX_COE_MODE bits.
MAC Control Register
simultaneously.
{DSAP, SSAP, CTRL,
2
OUI[23:16]}
Figure 3.23 Ethernet Frame with VLAN Tag and SNAP Header
8
1
0
0
4
OUI[23:16]}
V
I
D
8
1
0
0
3
8
1
0
0
V
I
D
5
L
e
n
V
I
D
4
L
e
n
S
N
A
P
0
6
S
N
A
P
0
5
S
N
A
P
1
7
S
N
A
P
1
6
8
(MAC_CR)) and vice versa. These functions cannot be enabled
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
{OUI[15:0], PID[15:0]}
DATASHEET
Checksum Offload Engine Control Register (COE_CR)
{OUI[15:0], PID[15:0]}
62
Calculate Checksum
Calculate Checksum
L3 Packet
L3 Packet
SMSC LAN9420/LAN9420i
C
F
S
F
C
S
enables the
Datasheet