LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 89

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
4.2.3
31:16
BITS
11:7
6:4
15
14
13
12
3
2
RESERVED
Software Interrupt (SW_INT)
This bit latches high upon the SW_INT_EN bit toggling from a 0 to 1. The
interrupt is cleared by writing a ‘1’. Writing ‘0’ has no effect.
RESERVED
Master Bus Error Interrupt (MBERR_INT)
When set, indicates DMA Controller has detected an error during descriptor
read, or during a transmit data read operation. The interrupt is cleared by
writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
To guarantee a clean recovery from a MBERR_INT condition, a software
reset must be performed by setting the
Bus Mode Register
cleared by a hardware reset.
Slave Bus Error Interrupt (SBERR_INT)
When set, indicates that the PCI Target Interface has detected an error
when the Host attempted to access the LAN9420/LAN9420i CSR. The
interrupt is cleared by writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
To guarantee a clean recovery from a SBERR_INT condition, a software
reset must be performed by setting the
Bus Mode Register
cleared by a hardware reset
RESERVED
GPIO [2:0] (GPIOx_INT)
Interrupts are generated from the GPIO’s. These interrupts are configured
through the GPIO_CFG register. Refer to
Input/Output Configuration Register (GPIO_CFG)," on page 92
information. These interrupts are cleared by writing a ‘1’ to the
corresponding bits. Writing ‘0’ has no effect.
GP Timer (GPT_INT)
This interrupt is issued when the General Purpose Timer wraps from
maximum count to zero. This interrupt is cleared by writing a ‘1’ to this bit.
Writing ‘0’ has no effect.
PHY Interrupt (PHY_INT)
Indicates assertion of the PHY Interrupt. The PHY interrupt is cleared by
clearing the interrupt source in the PHY Interrupt Status Register. Refer to
Section 4.5.11, "Interrupt Source Flag," on page 146
on this interrupt. Writing to this bit has no effect.
Interrupt Status Register (INT_STS)
This register contains the current status of the generated interrupts. Some of these interrupts are also
cleared through this register.
Offset:
(BUS_MODE). Alternatively, the condition may be
(BUS_MODE). Alternatively, the condition may be
DESCRIPTION
00C8h
DATASHEET
Software Reset (SRST)
Software Reset (SRST)
4.2.5, "General Purpose
89
Size:
for more information
for more
bit of the
bit of the
32 bits
R/WC
R/WC
R/WC
R/WC
R/WC
TYPE
RO
RO
RO
RO
Revision 1.4 (12-17-08)
DEFAULT
000b
0b
0b
0b
0b
0b
-
-
-