LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 76

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Revision 1.4 (12-17-08)
3.7.4.1.2
3.7.4.2
3.7.4.2.1
3.7.4.3
3.7.4.3.1
EXITING THE G3 STATE
When the system leaves the G3 state, the device will behave as follows. State transitions are illustrated
in
D0
In this state all internal clocks are enabled, but the device has not been initialized by the PCI Host.
The device cannot receive or transmit Ethernet data. Depending on the reason for the transition into
D0
are noted in the discussions that follow.
In D0
(PM_STATE)
indicate a setting of 00b (D0 state).
EXITING THE D0
The device will exit the D0
Figure 3.28 on page
D0
In this state all internal clocks are operational and the device is able to receive and transmit Ethernet
data. This is the normal operational state of the device.
In D0
(PM_STATE)
indicate a setting of 00b (D0 state).
POWER MANAGEMENT EVENTS IN D0
If configured to do so, the device is capable of detecting MAC (WOL, Magic Packet) and PHY (link
status change) wake events and is capable of asserting a PCI interrupt (nINT) or nPME as a result of
Figure 3.28 on page
U
UNINTIALIZED
ACTIVE
G3 to D3
supply and all power is off (PCInRST=X, PM_STATE=X, VAUXDET=0, PWRGOOD=0) and then
3.3Vaux is applied (PCInRST=0, PM_STATE=X, VAUXDET=0 to 1, PWRGOOD=0).
LAN9420/LAN9420i detects the application of auxiliary power and asserts its internal power-on
reset (POR). POR resets the
and Status Register (PCI_PMCSR)
the
internal PHY is held in the general-power down state and the device is powered by the PCI 3.3Vaux
supply. The device will remain in the D3
D0
Management State (PM_STATE)
(PCI_PMCSR). PCI main and auxiliary power (if used) remain on (PCInRST=1, PM_STATE=00b
to 11b, VAUXDET=X, PWRGOOD=1).
D0
configured by the PCI Host. (PCInRST=1, PM_STATE=00b, VAUXDET=X, PWRGOOD=1).
D0
Management State (PM_STATE)
(PCI_PMCSR)
turned off and 3.3Vaux is still operational (PCInRST=1, PM_STATE=00b, VAUXDET=1,
PWRGOOD=1 to 0). The internal PHY is reset and is placed in the General Power-Down mode on
this transition. Note that if VAUXDET=0, the device is being powered from the PCI +3.3V supply
and will turn off (G3) when PCI power is removed.
D0
PM_STATE=XXb, VAUXDET=1 to 0, PWRGOOD=1 to 0). For example, total power failure.
, the PHY may have been reset and may be in the General Power-Down state. These conditions
U
A
U
U
U
U
PCI Power Management Control and Status Register (PCI_PMCSR)
the device will respond to all PCI accesses. While in this state, the
the device will respond to all PCI accesses. While in this state, the
to D3
to D3
to D0
to G3 (T12): This transition occurs when all power supplies are turned off (PCInRST=X,
State (D0
COLD
HOT
COLD
A
field of the
field of the
(T2): This transition occurs when the device is in the D0
State (D0
U
(T1): This transition occurs when the Host system selects the “D3” state in the
(T6): This transition occurs when VAUXDET is connected to the PCI 3.3Vaux power
is set to “D0”, but the device has not yet been initialized, and then PCI power is
(T10): This transition occurs when all power supplies are operational and the
STATE
75.
A
75.
)
PCI Power Management Control and Status Register (PCI_PMCSR)
PCI Power Management Control and Status Register (PCI_PMCSR)
U
U
)
state under the following conditions. State transitions are illustrated in
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
PME Enable (PME_EN)
DATASHEET
field of the
field of the
and sets the
A
76
COLD
PCI Power Management Control and Status Register
PCI Power Management Control and Status Register
state until PCI power is applied.
Power Management State (PM_STATE)
bit of the
PCI Power Management Control
U
uninitialized state and is then
Power Management State
Power Management State
to the “D3” state. The
SMSC LAN9420/LAN9420i
Datasheet
field of
Power
Power
will
will