LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 58

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Revision 1.4 (12-17-08)
BITS
BITS
BITS
30:0
2:1
7:0
31
3
0
The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether
or not this is a wakeup frame.
The Filter i command register controls Filter i operation.
register.
The Filter i Offset register defines the offset in the frame’s destination address field from which the
frames are examined by Filter i.
The Filter i CRC-16 register contains the CRC-16 result of the frame that should pass Filter i.
Table 3.18
DESCRIPTION
RESERVED
Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte pattern-offset + j of
the incoming frame. Otherwise, byte pattern-offset + j is ignored.
DESCRIPTION
Address Type: Defines the destination address type of the pattern. When bit is set, the pattern
applies only to multicast frames. When bit is cleared, the pattern applies only to unicast frames.
RESERVED
Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled.
DESCRIPTION
Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wakeup frame
recognition. The MAC checks the first offset byte of the frame for CRC and checks to determine
whether the frame is a wakeup frame. Offset 0 is the first byte of the incoming frame's destination
address.
describes the Filter i CRC-16 bit fields.
Table 3.15 Filter i Byte Mask Bit Definitions
Table 3.16 Filter i Command Bit Definitions
Table 3.17 Filter i Offset Bit Definitions
FILTER i BYTE MASK DESCRIPTION
FILTER i OFFSET DESCRIPTION
Table
FILTER i COMMANDS
Table 3.17
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
3.15, describes the byte mask’s bit fields.
58
describes the Filter i Offset bit fields.
Table 3.16
shows the Filter I command
SMSC LAN9420/LAN9420i
Datasheet