COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 11

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Chapter 4
4.1
4.2
SMSC COM20022I
INTERNAL CLOCK
FREQUENCY
80 MHz
40 MHz
20 MHz
Network Protocol
Communication on the network is based on a token passing protocol. Establishment of the network
configuration and management of the network protocol are handled entirely by the COM20022I's internal
microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet
and its destination ID into the COM20022I's internal RAM buffer, and issuing a command to enable the
transmitter. When the COM20022I next receives the token, it verifies that the receiving node is ready by
first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits an ACKnowledge
message, the data packet is transmitted followed by a 16-bit CRC. If the receiving node cannot accept the
packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge message and the
transmitter passes the token. Once it has been established that the receiving node can accept the packet
and transmission is complete, the receiving node verifies the packet.
successfully, the receiving node transmits an ACKnowledge message (or nothing if it is not received
successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful
delivery of the packet. An interrupt mask permits the COM20022I to generate an interrupt to the processor
when selected status bits become true. Figure 2.1 is a flow chart illustrating the internal operation of the
COM20022I connected to a 20 MHz crystal oscillator.
Data Rates
The COM20022I is capable of supporting data rates from 156.25 Kbps to 10 Mbps. The following protocol
description assumes a 10 Mbps data rate. To attain the faster data rates, the clock frequency may be
doubled or quadrupled by the internal clock multiplier (see next section). For slower data rates, an internal
clock divider scales down the clock frequency. Thus all timeout values are scaled as shown in the
following table:
Example:
IDLE LINE Timeout @ 10 Mbps = 20.5 μs. IDLE LINE Timeout for 156.2 Kbps is 20.5 μs * 64 = 1.3 ms
CLOCK PRESCALER
Protocol Description
Div. by 128
Div. by 16
Div. by 32
Div. by 64
Div. by 8
Div. by 8
Div. by 8
DATASHEET
Page 11
DATA RATE
156.25 Kbps
312.5 Kbps
1.25 Mbps
625 Kbps
2.5 Mbps
10 Mbps
5 Mbps
TIMEOUT SCALING FACTOR
(MULTIPLY BY)
If the packet is received
16
32
64
1
2
4
8
Revision 09-27-07