COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 80

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

Revision 09-27-07
The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the Setup1
register. The CKP3-1 bits are changed by writing the Setup1 register from outside the CPU. It's not
synchronized between the CPU and COM20022I. Thus, changing the CKP2-0 timing does not synchronize
with the internal clocks of Pre-Scalar, and changing CKP2-0 may cause spike noise to appear on the
output clock line.
Setting the EF bit will include flip-flops inserted between the Setup1 register and Pre-Scalar for
synchronizing the CKP2-0 with Pre-Scalar’s internal clocks.
Never change the CKP2-0 when the data rate is over 5 Mbps. They must all be zero.
The COM20022I limits the write interval time for continuous writing to the Command register. The
minimum interval time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 μ S at the 156.25
Kbps. This 1.6 μ S is very long for CPU.
Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to XTAL
clock which is not changed by the data rate, such that the minimum interval time becomes 100 nS.
The COM20022I has a write prohibition period for writing the Enable Transmit/Receive Commands. This
period is started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by
setting the TA/RI bit with an internal pulse signal. It is 3.2 μ S at 156.25 Kbps. This period may be a
problem when using interrupt processing. The interrupt occurs when the RI bit returns to High. The CPU
writes the next Enable Receive Command to the other page immediately. In this case, the interval time
between the interrupt and writing Command is shorter than 3.2 μ S.
Setting the EF bit will cause the TA/RI bit to return to High upon release of the internal pulse signal for
setting the TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 10.1 on the following
page.
b)
c)
d)
Synchronize the Pre-Scalar Output
Shorten The Write Interval Time To The Command Register
Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
DATASHEET
Page 80
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
SMSC COM20022I
Datasheet