COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 63

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I
Figure 8.5
nIOCS16
A0-A2
D0-D15
nCS
nWR
nRD
*
**
***
****
Note 1:
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
T
T
T
T
ARB
ARB
ARB
opr
t10
t11
t12
- Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
nCS may become active after control becomes active, but the access time (t6)
will now be 45nS measured from the leading edge of nCS.
t11 is measured from the latest active (valid) timing among nCS, A0-A2.
t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
t1
t2
t3
t4
t5
t6
t7
t8
t9
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Data Register requires a minimum of 5T
leading edge of the next nRD.
Data Register requires a minimum of 5T
leading edge of nRD.
nRD Low Width
nRD High Width
nWR
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
opr
CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0
if SLOW ARB = 1
to nRD Low
Note 3
opr
t1
t10
if SLOW ARB = 0
DATASHEET
t3
Parameter
t11
Page 63
t6
VALID
ARB
ARB
from the trailing edge of nRD to the
from the trailing edge of nWR to the
t8
VALID VALUE
VALID DATA
t5
4T
min
15
10
ARB
5**
0
60
20
20
0****
0
*
max
40**
40***
20
t7
t2
t4
Note 2
t9
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t12
Revision 09-27-07