COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 28

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

5.2.3
5.2.4
Revision 09-27-07
Differential Driver Configuration
The Differential Driver Configuration is a special case of the Backplane Mode.
configuration recommended for applications like car-area networks or other cost-sensitive applications
which do not require direct compatibility with existing ARCNET nodes and do not require isolation. The
Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid
Configuration. Like the Backplane Configuration, the Differential Driver Configuration does not isolate the
node from the media.
The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable
and the COM20022I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is
active. The nPULSE1 signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of
pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20022I is
disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive.
Programmable TXEN Polarity
To accommodate transceivers with active high ENABLE pins, the COM20022I contains a programmable
TXEN output. To program the TXEN pin for an active high pulse, the nPULSE2 pin should be connected
to ground. To retain the normal active low polarity, nPULSE2 should be left open.
determination is made at power on reset and is valid only for Backplane Mode operation. The nPULSE2
pin should remain grounded at all times if an active high polarity is desired.
nWR/DIR
nRD/nDS
AD0-AD2,
nIOCS16
D3-D15
nRESET
nINTR
nCS
ARBITRATION
CIRCUITRY
CIRCUITRY
DECODING
ADDRESS
BUS
LOGIC
RESET
Figure 5.10
COMMAND
REGISTER
STATUS/
RECONFIGURATION
DATASHEET
TIMER
- Internal Block Diagram
SEQUENCER
REGISTERS
WORKING
MICRO-
Page 28
AND
2K x 8
RAM
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
NODE ID
LOGIC
OSCILLATOR
TX/RX
LOGIC
ADDITIONAL
REGISTERS
DMA
XTAL1
nPULSE1
nPULSE2
nTXEN
RXIN
XTAL2
It is a dc coupled
nDACK
TC
nREFEX
DREQ
SMSC COM20022I
The polarity
Datasheet