COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 62

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

Revision 09-27-07
AD0-AD2,
D3-D15
nCS
nIOCS16
ALE
nWR
nRD
**
*
Note 1:
Note 2:
Note 3:
T
T
T
T
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
ARB
ARB
ARB
opr
Figure 8.4
t10
t11
t12
t13
t14
t15
t1
t2
t3
t4
t5
t6
t7
t8
t9
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
ALE High Width
ALE Low Width
nWR Low Width
nWR High Width
nRD
nIOCS16 Hold Delay from ALE Low
nIOCS16 Output Delay from ALE Low
Valid Data Setup to nDS High
Data Hold from nDS High
Cycle Time (nWR
Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5T
leading edge of nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5T
leading edge of the next nWR.
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4T
next nWR.
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Previous Value
opr
- Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
if SLOW ARB = 1
t9
to nWR Low
t1
opr
VALID
t3
if SLOW ARB = 0
t13
ARB
MUST BE: BUSTMG pin = HIGH
Note 3
Parameter
from the trailing edge of nWR to the leading edge of the
t14
t2,
t4
to Next
t5
DATASHEET
Invalid
t15
)**
ARB
ARB
Page 62
from the trailing edge of nRD to the
from the trailing edge of nWR to the
t10
t11
VALID DATA
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
t6
4T
min
20
20
20
20
20
30
10
Valid Value
20
10
10
10
15
0
ARB
*
max
40
t7
Note 2
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t8**
t12
t8
SMSC COM20022I
Datasheet