COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 42

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

Revision 09-27-07
BIT
4,3
1,0
7
6
5
2
Reset
Command
Chaining Enable
Transmit Enable
Extended
Timeout 1,2
Backplane
Sub Address 1,0
BIT NAME
RESET
CCHEN
TXEN
ET1, ET2
BACK-
PLANE
SUBAD 1,0
SYMBOL
Table 6.9 - Configuration Register
DATASHEET
A software reset of the COM20022I is executed by writing a logic
"1" to this bit. A software reset does not reset the microcontroller
interface mode, nor does it affect the Configuration Register. The
only registers that the software reset affect are the Status
Register, the Next ID Register, and the Diagnostic Status
Register. This bit must be brought back to logic "0" to release the
reset.
This bit, if high, enables the Command Chaining operation of the
device. Please refer to the Command Chaining section for further
details. A low level on this bit ensures software compatibility with
previous SMSC ARCNET devices.
When low, this bit disables transmissions by keeping nPULSE1,
nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive.
When high, it enables the above signals to be activated during
transmissions. This bit defaults low upon reset. This bit is
typically enabled once the Node ID is determined, and never
disabled during normal operation. Please refer to the Improved
Diagnostics section for details on evaluating network activity.
These bits allow the network to operate over longer distances
than the default maximum 1 mile by controlling the Response,
Idle, and Reconfiguration Times. All nodes should be configured
with the same timeout values for proper network operation. For
the COM20022I with a 20 MHz crystal oscillator, the bit
combinations follow:
Note: These values are for 10Mbps and RCNTMR[1,0]=00.
A logic "1" on this bit puts the device into Backplane Mode
signaling which is used for Open Drain and Differential Driver
interfaces.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD1
See also the Sub Address Register.
ET2
0
0
1
1
0
0
1
1
Page 42
Reconfiguration time is changed by the RCNTMR1 and
RCNTMR0 bits.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
ET1
SUBAD0
0
1
0
1
0
1
0
1
DESCRIPTION
Response
Time ( μ S)
298.4
149.2
74.7
18.7
Tentative ID
Node ID
Setup 1
Next ID
Register
Idle Time
( μ S)
328
164
82
20.5
SMSC COM20022I
Reconfig
Time
(mS)
420
420
420
210
Datasheet