COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 66

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

Revision 09-27-07
nIOCS16
D0-D15
Figure 8.8
A0-A2
DIR
nDS
nCS
Note 1:
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
*
**
*** t12 is measured from the latest active (valid) timing among nCS, A0-A2.
****
Note 2 is applied to an access to Data Register by DMA transfer.
T
T
T
T
t10
t11
t12
t13
ARB
ARB
ARB
opr
t6
t1
t2
t3
t4
t5
t7
t8
t9
t8 is measured from the latest active (valid) timing among nCS, nDS, A0-A2.
t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
- Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
to Data Register requires a minimum of 5T
the leading edge of the next nDS.
Address Setup to nDS Active
nCS Setup to nDS Active
nCS Hold from nDS Inactive
Address Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)
DIR Hold from nDS Inactive
nDS Low to Valid Data
nDS High to Data High Impedence
nDS Low Width
nDS High Width
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
opr
CASE 2: BUSTMG pin = LOW or RBUSTMG bit = 1
if SLOW ARB = 1
opr
t1
if SLOW ARB = 0
DATASHEET
t5
t3
Parameter
t12
Page 66
t8
VALID
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
ARB
VALID VALUE
from the trailing edge of nDS to
t10
t6
VALID DATA
4T
min
ARB
100
0****
10
10
30
-5
-5
0
0
0
*+30
max
60**
40***
20
t9
t7
t2
t4
Note 2
t11
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t13
SMSC COM20022I
Datasheet