RC82562EP Intel, RC82562EP Datasheet - Page 137
RC82562EP
Manufacturer Part Number
RC82562EP
Description
IC ETH 10/100 PLC DEV CTRL 64BGA
Manufacturer
Intel
Specifications of RC82562EP
Rohs Status
RoHS non-compliant
Controller Type
Ethernet Controller
Interface
IEEE 802.3
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
64-BGA
Current - Supply
-
Operating Temperature
-
Other names
832361
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7.4.2
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 61. Technology Ability Field Bit Assignments
Table 62. Technology Priority
To detect the correct technology, the two register fields are ANDed together to obtain the highest
common denominator. This value is used to map into a priority resolution table used by the MAC
driver to select the appropriate technology. The auto-negotiation process occurs in the following
steps:
Parallel Detection
The key to auto-negotiation’s interoperation with installed legacy LANs is the Parallel Detection
function. Parallel Detection can be used to determine what the line speed is if the link partner does
not support an N-Way (the FLP exchange is not supported) repeater or switch. Parallel Detection
works by passing the signals present on the receiver to the 100BASE-TX and 100BASE-T4 link
monitor functions. If one link monitor function indicates a valid link, then it connects that
technology to the media.
The 82555 PHY and the 8255x (excluding the 82557) PHY modules support N-Way and Parallel
Detection (in the event that their link partner does not respond to FLPs).
Bit Setting
0
1
2
3
4
5
6
7
Priority
1
2
3
4
5
1. Receive 3 consecutive, matching code words.
2. Set acknowledge bit in transmit code word.
3. Receive 3 consecutive, matching code words with acknowledge bit set.
4. Transmit 6 to 8 more code words with acknowledge bit set.
5. Use priority table to determine operating mode.
6. FLP received from link partner is recorded in MDI register.
Technology
10BASE-T
10BASE-T Full Duplex
100BASE-TX
100BASE-TX Full Duplex
100BASE-T4
Reserved
Reserved
Reserved
Technology
100BASE-TX Full Duplex
100BASE-T4
100BASE-TX
10BASE-T Full Duplex
10BASE-T
Physical Layer Interface
129
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