RC82562EP Intel, RC82562EP Datasheet - Page 157

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

A.7.4
A.7.4.1
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 65. Dump Data Structure
Note: The port dump wake-up packet causes an internal selective reset to the 82559.
Note: The interesting packet bit in the PMDR is set together with the PME status bit when an interesting
Note: The 82559 uses the statistic counters resources to store the wake-up packet. The software driver
Note: Magic Packets are exceptional to all other wake-up packets. The Magic Packets may cause a power
The sequence of events after a Dump Wake-up command that the 82559 performs are:
Prior to the Dump Wake-up packet command, the driver should first initialize the status word to 0.
After the Dump Wake-up packet command, it should pole the Status word for the Complete bit.
packet is received.
should assume that the statistic counters are infected at power down state. Therefore, it should
issue a Dump Reset Statistic Counters command before it resumes nominal operation.
management event and set an indication bit in the PMDR. However, it is not stored by the 82559
for system use when it is awake. The 82559ER does not support Magic Packet wake up.
Power Management Software Flow
The 82559 adheres to the PCI Power Management Specification supporting all three power states
D0 through D3. This section describes the required flow of events for software to set the 82559 into
the power down states.
Power Down without Wake-up Capabilities
The 82559 supports a very low power state if wake-up capabilities are not required. The OS should
follow these steps:
1. Write the byte count field at Dword 1. This field contains the actual number of bytes posted in
2. Write the wake-up packet data starting at Dword 2.
3. Write a status word composed of the Complete OK bits equal to A000h at Dword 0.
1. Clear the PME enable bit in the PMCSR to the PME disable state.
2. Set the 82559 to the D3 power state (by OS).
Offset
2:N
the host memory. A value of FFh indicates that the Wake-up packet length exceeded the 120
bytes. In this case only the first 120 bytes are posted.
Note:
0
1
D31
Step 2 may be executed together with step 1 (same cycle) but not before. If step 2
is executed before step 1, the 82559 might assert PME# if wake on link status
change is enabled. At this state, the 82559 enters the deep power down state, where
the PHY is turned off. At this state, the 82559 consume less than 7 mA if the PCI
Reserved
Reserved
Wake-up Packet
Status Word (A000h)
Wake-up Functionality
Byte Count
D0
149