RC82562EP Intel, RC82562EP Datasheet - Page 74
RC82562EP
Manufacturer Part Number
RC82562EP
Description
IC ETH 10/100 PLC DEV CTRL 64BGA
Manufacturer
Intel
Specifications of RC82562EP
Rohs Status
RoHS non-compliant
Controller Type
Ethernet Controller
Interface
IEEE 802.3
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
64-BGA
Current - Supply
-
Operating Temperature
-
Other names
832361
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Table 40. 82557 Dual-Port FIFO Settings
Table 41. 82558 and 82559 Dual-Port FIFO Settings
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
a.
NOTE: The configuration values are from 0 through Fh. The table shows the values in binary (4 bits wide).
a.
•
•
Binary (Transmit Bits 6:4 & Receive Bits 3:0)
This line represents the default values.
This line represents the default values.
BYTE 2: Adaptive IFS. This byte indicates the minimum number of PCI clocks counted
between sending two transmit frames on the wire. The resolution of this counter is 8 PCI
clocks making the range from 0 to 2040 PCI clocks.
Default - 0.
Recommended - 0.
BYTE 3.
— Bit 3 - Terminate Write on Cache Line. This bit is reserved on the 82557 and should be set
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
to 0.
However, when this bit is set on the 82558 or a later generation controller, the device
attempts to terminate its write accesses on cache lines. This may yield lower PCI
throughput in systems which are not extremely cache line oriented. This bit should
therefore be set only in systems that are extremely cache line oriented.
0 = Terminate Write on Cache Line disabled.
Configuration Value
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Dwords
Transmit FIFO Limit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
5
6
7
Bytes
12
16
20
24
28
12
16
20
24
28
16
20
24
28
0
4
8
0
4
8
Dwords
Receive FIFO Limit
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
4
3
2
1
Bytes
128
120
104
112
64
96
88
80
72
56
48
40
32
24
16
16
12
8
8
4
a
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