RC82562EP Intel, RC82562EP Datasheet - Page 83

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
•
Similarly, the value at offset 14 of the configuration block is compared to the byte at offset 40
in ARP frames without a VLAN header and to byte 44 in ARP frames with a VLAN header.
The 16-bit value of the IP address in the configuration block is in non-canonical format, while
the IP address of an ARP frame is stored in canonical format. Using the same IP address in the
example above (012h 034h 056h 078h), the ARP filter performs the following comparison:
Table 45. 82558 B-step ARP Frame IP Address Mapping
Although this field is not present in the 82559, its functionality is present in the extended
wake-up packet command.
Default - 00h, F2h (for backward compatibility).
BYTE 15.
— Bit 7 - CRS or CDT. When this bit is set, the device will interpret an active CDT during
— Bit 5 - CRC16.
— Bit 4 - Ignore U/L. This bit is reserved on the 82557 and should be set to 0. When this bit
— Bit 2 - Wait After Win. This bit is reserved on the 82557 and should be set to 0. For the
transmission as an active carrier.
0 = CRS only.
1 = CRS or CDT.
Default - 1.
Recommended - 1 for 82557/82503 based designs, 0 for 82557/MII based designs, 0 for
82558 or 82559 based designs.
This bit selects the 16-bit or 32-bit CRC engine. When it is set to 1, the 82559 operates
with a 16-bit CRC generator. Clearing this bit selects the 32-bit CRC engine. (Ethernet
operates with a 32-bit CRC.)
0 = 32-bit CRC.
1 = 16-bit CRC.
Default - 0.
Recommended - 0 (must be 0).
is set on the 82558 or 82559, the device ignores the U/L bit when checking for IA match
on received frames.
0 = Consider U/L bit.
1 = Ignore U/L bit.
Default - 0 (Consider U/L bit).
Recommended - 0.
82558 or 82559, it activates the modified backoff algorithm, Wait After Win
“Collision Backoff Modification in Switched
0 = Wait After Win disabled.
1 = Wait After Win enabled.
Configuration Block
Block Offset
Example Value
Frame Offset
Incoming Frame
Offset 13
IP Address Low
078h
40
Environments”).
Offset 14
IP Address High
056h
41
Host Software Interface
(Section 6.7,
75