RC82562EP Intel, RC82562EP Datasheet - Page 85

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
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BYTE 18.
Bits 6:4 - Priority Flow Control Threshold. These bits are reserved on the 82557 and should be
set to 111.
For the 82558 or 82559, this three-bit field defines the threshold at which the device
differentiates between Pause and Pause Low FC frames
Control
Threshold” is considered Pause_Low. Setting this configuration field to any value other than
the default 111 activates the Priority FC mode.
Default - 111 (disabled).
Recommended - 111 (unless the priority flow control threshold mechanism is implemented).
BYTE 19.
Table 46. Full Duplex Functionality
— Bit 0 - Stripping Enable. If this bit is set to 1, the device enables the stripping mechanism.
— Bit 7 - Full Duplex Pin Enable. When this bit is set, the device examines the FDX# pin to
byte (7Eh) will be transmitted to pad (in other words, fill) the minimum frame length. The
CRC will include the padded bytes. If padding is disabled, no padding bytes will be added
even if the frame is a short frame.
Default - 1 (enabled).
Recommended - 1.
If the byte count of a received frame is lower than the actual length received, every byte
beyond the specified length will be stripped from the frame except the CRC. If it is set to
0, no stripping will be performed.
Stripping is performed only on frames that have the Length/Type field set to Length (0 <
value
Default - 0 (disabled).
Recommended - 1. However, it should be avoided if the minimum packet length cannot be
safely assumed.
determine if it should operate in full duplex or half duplex mode. If the force full duplex
bit (bit 6) is set to one, then this bit has no meaning and the device will not examine the
level of the FDX# pin. This is described in the table below.
Default - 0 (off) for the 82557 and 82558 A -step; 1 (on) for the 82558 B-step and 82559.
Recommended - 1.
Operation”). Every FC frame with “priority field” greater than “Priority FC
1500).
FDX PIN ENABLE
(bit 7)
0
1
0
1
0
1
0
1
FORCE FDX
(bit 6)
0
0
1
1
0
0
1
1
State of FDX#
(Section 6.6.3.1, “Priority Flow
0
0
0
0
1
1
1
1
Host Software Interface
Device Operating
Half Duplex
Half Duplex
Half Duplex
Full Duplex
Full Duplex
Full Duplex
Full Duplex
Full Duplex
Mode
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