RC82562EP Intel, RC82562EP Datasheet - Page 69

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

6.4.2.3
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Figure 17. Configure Command Format
The individual address is transferred by the transmit DMA through the transmit FIFO to the
execution machine in the CSMA/CD module. Therefore, it may take some time to execute. The
execution unit maintains a 48-bit individual address register used for source address insertion
during transmission and for destination address recognition during reception. A reset causes the
individual address register to be set to FF FF FF FF FF FFh.
After reading the command and determining whether it is an IA setup command, the device CU
performs the following sequence:
Configure (010b)
The configure command loads the device with its operating parameters. A maximum of 22
configuration bytes are supported. The first eight bytes are used by the CU, and the remaining
bytes are passed to the CSMA/CD unit through the transmit DMA. The minimum number of
configuration bytes is 8.
Parameters not configured automatically use default values. The only exception is the PHY
interface configuration bit. For 82557 based adapters, this bit must be set to either a zero or one
before the 82557 will transmit or receive frames. For 82558 and later generation controllers, this
bit must be set to 1 before the device will send and receive.
The individual bit fields of the configure command is another area where there are numerous
differences between the controllers (82557, 82558, 82559, etc.). Therefore, a complete
configuration map for each device will be presented below. Bit descriptions for the configuration
bits follow the configuration map.
00h
04h
08h
0Ch
10h
14h
18h
1Ch
1. Begins execution of the IA setup action command.
2. Initiates the transmit DMA with the address of the first byte of the individual address and a
3. Waits for the transmit byte machine to complete the internal update of the individual address
4. Completes the IA setup action command.
Offset
byte count of 6.
register.
EL
Link Address (A31:A0)
Byte 3
Byte 7
Byte 11
Byte 15
Byte 19
00 00 00 00
S
Command Word Bits 31:16
I
0000000000
Byte 2
Byte 6
Byte 10
Byte 14
Byte 18
00 00 00 00
010
C
Byte 1
Byte 5
Byte 9
Byte 13
Byte 17
Byte 21
X
Status Word Bits 15:0
OK
XXXXXXXXXXXXX
Host Software Interface
Byte 0
Byte 4
Byte 8
Byte 12
Byte 16
Byte 20
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