DP83848TSQ/NOPB National Semiconductor, DP83848TSQ/NOPB Datasheet - Page 20

• Manufacturer Part Number: DP83848TSQ/NOPB
• Description: IC TXRX ETHERNET PHYTER 40-LLP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83848TSQ/NOPB

• Number Of Drivers/receivers: 1/1
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: LLP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 2 - 1 Year
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• Driver Case Style: LLP
• For Use With: DP83848T-MAU-EK - BOARD EVALUATION DP83848T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DP83848TSQTR

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3.0 Functional Description
The DP83848T supports two modes of operation using
the MII interface pins. The options are defined in the fol-
lowing sections and include:
— MII Mode
— RMII Mode
The modes of operation can be selected by strap options
or register control. For RMII mode, it is required to use the
strap option, since it requires a 50 MHz clock instead of
the normal 25 MHz.
In the each of these modes, the IEEE 802.3 serial man-
agement interface is operational for device configuration
and status. The serial management interface of the MII
allows for the configuration and control of multiple PHY
devices, gathering of status, error information, and the
determination of the type and capabilities of the attached
PHY(s).
3.1 MII Interface
The DP83848T incorporates the Media Independent Inter-
face (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describes the nibble wide MII data interface.
The nibble wide MII data interface consists of a receive
bus and a transmit bus each with control signals to facili-
tate data transfer between the PHY and the upper layer
(MAC).
3.1.1 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface includes a
dedicated receive bus and a dedicated transmit bus.
These two data buses, along with various control and sta-
tus signals, allow for the simultaneous exchange of data
between the DP83848T and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus
RXD[3:0], a receive error signal RX_ER, a receive data
valid flag RX_DV, and a receive clock RX_CLK for syn-
chronous transfer of the data. The receive clock operates
at either 2.5 MHz to support 10 Mb/s operation modes or
at 25 MHz to support 100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus
TXD[3:0], a transmit enable control signal TX_EN, and a
transmit clock TX_CLK which runs at either 2.5 MHz or 25
MHz.
Additionally, the MII includes the carrier sense signal
CRS, as well as a collision detect signal COL. The CRS
signal asserts to indicate the reception of data from the
network or as a function of transmit data in Half Duplex
mode. The COL signal asserts as an indication of a colli-
sion which can occur during half-duplex operation when
both a transmit and receive operation occur simulta-
neously.
3.1.2 Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is
detected when the receive and transmit channels are
20
active simultaneously. Collisions are reported by the COL
signal on the MII.
If the DP83848T is transmitting in 10 Mb/s mode when a
collision is detected, the collision is not reported until
seven bits have been received while in the collision state.
This prevents a collision being reported incorrectly due to
noise on the network. The COL signal remains set for the
duration of the collision.
If a collision occurs during a receive operation, it is imme-
diately reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1µs after the transmission of
each packet, a Signal Quality Error (SQE) signal of
approximately 10 bit times is generated (internally) to indi-
cate successful transmission. SQE is reported as a pulse
on the COL signal of the MII.
3.1.3 Carrier Sense
Carrier Sense (CRS) is asserted due to receive activity,
once valid data is detected via the squelch function during
10 Mb/s operation. During 100 Mb/s operation CRS is
asserted when a valid link (SD) and two non-contiguous
zeros are detected on the line.
For 10 or 100 Mb/s Half Duplex operation, CRS is
asserted during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is
asserted only due to receive activity.
CRS is deasserted following an end of packet.
3.2 Reduced MII Interface
The DP83848T incorporates the Reduced Media Indepen-
dent Interface (RMII) as specified in the RMII specification
(rev1.2) from the RMII Consortium. This interface may be
used to connect PHY devices to a MAC in 10/100 Mb/s
systems using a reduced number of pins. In this mode,
data is transferred 2-bits at a time using the 50 MHz
RMII_REF clock for both transmit and receive. The follow-
ing pins are used in RMII mode:
— TX_EN
— TXD[1:0]
— RX_ER (optional for Mac)
— CRS_DV
— RXD[1:0]
— X1 (RMII Reference clock is 50 MHz)
In addition, the RMII mode supplies an RX_DV signal
which allows for a simpler method of recovering receive
data without having to separate RX_DV from the CRS_DV
indication. This is especially useful for systems which do
not require CRS, such as systems that only support fulldu-
plex operation. This signal is also useful for diagnostic
testing where it may be desirable to loop Receive RMII
data directly to the transmitter.
Since the reference clock operates at 10 times the data
rate for 10 Mb/s operation, transmit data is sampled every
10 clocks. Likewise, receive data will be generated every