DP83848TSQ/NOPB National Semiconductor, DP83848TSQ/NOPB Datasheet - Page 22

• Manufacturer Part Number: DP83848TSQ/NOPB
• Description: IC TXRX ETHERNET PHYTER 40-LLP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83848TSQ/NOPB

• Number Of Drivers/receivers: 1/1
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Data Rate: 100Mbps
• Supply Voltage Range: 3V To 3.6V
• Logic Case Style: LLP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 2 - 1 Year
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 10Mbps
• Driver Case Style: LLP
• For Use With: DP83848T-MAU-EK - BOARD EVALUATION DP83848T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DP83848TSQTR

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3.3.3 Serial Management Preamble Suppression
The DP83848T supports a Preamble Suppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, address 01h.) If the station management
entity (i.e. MAC or other management controller) deter-
mines that all PHYs in the system support Preamble Sup-
pression by returning a one in this bit, then the station
management entity need not generate preamble for each
management transaction.
The DP83848T requires a single initialization sequence of
32 bits of preamble following hardware/software reset.
MDIO
MDIO
MDC
MDC
MDIO
(STA)
(PHY)
(STA)
Z
Idle
Z
Idle
Z
Z
0
0
Start
Start
1 1
1
Opcode
Opcode
(Read)
(Write)
0
0 0
1
0
(PHYAD = 0Ch)
(PHYAD = 0Ch)
PHY Address
PHY Address
1 1 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
Figure 5. Typical MDC/MDIO Write Operation
Figure 4. Typical MDC/MDIO Read Operation
Register Address
Register Address
(00h = BMCR)
(00h = BMCR)
Z
Z
Z
22
1
TA
0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
TA
0 0 0
This requirement is generally met by the mandatory pull-
up resistor on MDIO in conjunction with a continuous
MDC, or the management access made to determine
whether Preamble Suppression is supported.
While the DP83848T requires an initial preamble
sequence of 32 bits for management initialization, it does
not require a full 32-bit sequence between each subse-
quent transaction. A minimum of one idle bit between
management transactions is required as specified in the
IEEE 802.3u specification.
0 0
0 0 0
Register Data
Register Data
0
0 0 0 0 0 0 0 0
Z
Idle
Z
Z
Idle
Z