PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet - Page 118

• Manufacturer Part Number: PIC24FJ64GA006-I/PT
• Description: 64 PIN, 64KB FLASH, 8 KB RAM, 53 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA006-I/PT

• A/d Inputs: 16 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 53
• Number Of Pins: 64
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 16 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ128GA FAMILY
To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1.
2.
3.
4.
5.
6.
FIGURE 14-1:
DS39747C-page 116
a)
b)
c)
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 1.
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
If using interrupts:
Clear the SPIROV bit (SPIxSTAT<6>).
Note 1: In Standard modes, data is transferred directly between SPIxSR and SPIxBUF.
SDOx
SCKx
SDIx
SSx
Clear the SPIxIF bit in the respective IFSn
register.
Set the SPIxIE bit in the respective IECn
register.
Write the SPIxIP bits in the respective IPCn
register.
Read SPIxBUF
Control
Sync
Transfer
registers
SPI MODULE BLOCK DIAGRAM
bit0
8-Level FIFO Buffer
(Enhanced Modes)
SPIxBUF
with
SPIxSR
Control
Clock
Shift Control
(1)
MSTEN
Transfer
Write SPIxBUF
Preliminary
Select
Edge
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
16
Clear the SPIxBUF register.
If using interrupts:
• Clear the SPIxIF bit in the respective IFSn
• Set the SPIxIE bit in the respective IECn
• Write the SPIxIP bits in the respective IPCn
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Secondary
register.
register.
register to set the interrupt priority.
Prescaler
1:1 to 1:8
Internal Data Bus
registers
1:1/4/16/64
Prescaler
Primary
© 2006 Microchip Technology Inc.
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
with
F
CY
MSTEN