PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet - Page 129

• Manufacturer Part Number: PIC24FJ64GA006-I/PT
• Description: 64 PIN, 64KB FLASH, 8 KB RAM, 53 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA006-I/PT

• A/d Inputs: 16 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 53
• Number Of Pins: 64
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 16 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 15-1:
© 2006 Microchip Technology Inc.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
.
Upper Byte:
bit 15
I2CEN
R/W-0
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
ACKDT: Acknowledge Data bit (When operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(When operating as I
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiate Stop condition on SDAx and SCLx pins
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enabled bit (when operating as I
1 = Initiate Repeated Start condition on SDAx and SCLx pins
0 = Repeated Start condition not in progress
SEN: Start Condition Enabled bit (when operating as I
1 = Initiate Start condition on SDA and SCL pins
0 = Start condition not in progress
Legend:
R = Readable bit
-n = Value at POR
Hardware clear at end of master Acknowledge sequence.
Hardware clear at end of eighth bit of master receive data byte.
Hardware clear at end of master Repeated Start sequence.
Hardware clear at end of master Start sequence.
Hardware clear at end of master Stop sequence.
U-0
—
Lower Byte:
bit 7
GCEN
R/W-0
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
I2CSIDL
R/W-0
2
STREN
C master. Applicable during master receive.)
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-1 HC
SCLREL
2
C
ACKDT
R/W-0
Preliminary
IPMIEN
R/W-0
U = Unimplemented bit, read as ‘0’
HS = Set in Hardware
‘0’ = Bit is cleared
PIC24FJ128GA FAMILY
R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC
ACKEN
2
C master)
2
2
C master. Applicable during master receive.)
C master)
2
R/W-0
A10M
C master)
RCEN
2
C slave)
DISSLW
2
R/W-0
C master)
HC = Cleared in Hardware
x = Bit is unknown
PEN
SMEN
R/W-0
bit 8
RSEN
DS39747C-page 127
SEN
bit 0