PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet - Page 127

• Manufacturer Part Number: PIC24FJ64GA006-I/PT
• Description: 64 PIN, 64KB FLASH, 8 KB RAM, 53 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA006-I/PT

• A/d Inputs: 16 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 53
• Number Of Pins: 64
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 16 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.2
To compute the Baud Rate Generator reload value, use
the following equation:
EQUATION 15-1:
TABLE 15-1:
© 2006 Microchip Technology Inc.
Legend: Shaded rows represent invalid reload values for a given F
Note 1:
Note 1: Based on T
2:
3:
4:
Required
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
System
Setting Baud Rate When
Operating as a Bus Master
1 MHz
1 MHz
1 MHz
F
PLL are disabled.
SCL
Based on T
This is closest value to 400 kHz for this value of F
F
I2CxBRG cannot have a value of less than 2.
CY
or
F
I2CxBRG
= 2 MHz is the minimum input clock frequency to have F
SCL
I
2
(1)
C™ CLOCK RATES
=
CY
CY
--------------------------------------------- -
2
⋅
=
= F
= F
(
I2CxBRG
⎛
⎝
------------------ -
2 F
OSC
OSC
F
⋅
F
CY
CY
16 MHz
16 MHz
16 MHz
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
/2, Doze mode and PLL are disabled.
SCL
/2, Doze mode and
F
CY
⎞
⎠
+
–
1
)
1
(1)
Preliminary
(Decimal)
PIC24FJ128GA FAMILY
79
39
19
19
9
4
2
7
3
1
I2CxBRG Value
CY
15.3
The I2CxMSK register (Register 15-3) designates
address bit positions as “don’t care” for both 7-bit and
10-bit Address modes. Setting a particular bit location
(= 1) in the I2CxMSK register causes the slave module
to respond whether the corresponding address bit
value is a ‘0’ or ‘1’. For example, when I2CxMSK is set
to ‘00100000’, the slave module will detect both
addresses ‘0000000’ and ‘00100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
.
SCL
(Hexadecimal)
SCL
Slave Address Masking
and F
= 1 MHz.
4F
27
13
13
9
4
2
7
3
1
CY
.
333 kHz
DS39747C-page 125
1 MHz
1 MHz
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
Actual
1 MHz
F
SCL
(3)
(4)
(2)