PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet - Page 125

• Manufacturer Part Number: PIC24FJ64GA006-I/PT
• Description: 64 PIN, 64KB FLASH, 8 KB RAM, 53 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA006-I/PT

• A/d Inputs: 16 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 53
• Number Of Pins: 64
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 16 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.0
The Inter-Integrated Circuit (I
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, display drivers, A/D
converters, etc.
The I
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the I
• Clock stretching to provide delays for the
• Both 100 kHz and 400 kHz bus specifications.
• Configurable address masking
• Multi-Master modes to prevent loss of messages
• Bus Repeater mode, allowing the acceptance of
• Automatic SCL
A block diagram of the module is shown in Figure 15-1.
© 2006 Microchip Technology Inc.
Note:
processor to respond to a slave data request
in arbitration
all messages as a slave regardless of the address
2
C module supports these features:
INTER-INTEGRATED CIRCUIT
(I
2
This data sheet summarizes the features
of this group of PIC24FJ devices. It is not
intended to be a comprehensive reference
source.
C™)
2
C) module is a serial
2
C protocol
Preliminary
PIC24FJ128GA FAMILY
15.1
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for and verify an Acknowledge from the
11. Enable master reception to receive serial
12. Generate an ACK or NACK condition at the end
13. Generate a Stop condition on SDAx and SCLx.
Assert a Start condition on SDAx and SCLx.
Send the I
with a write indication.
Wait for and verify an Acknowledge from the
slave.
Send the first data byte (sometimes known as
the command) to the slave.
Wait for and verify an Acknowledge from the
slave.
Send the serial memory address low byte to the
slave.
Repeat steps 4 and 5 until all data bytes are
sent.
Assert a Repeated Start condition on SDAx and
SCLx.
Send the device address byte to the slave with
a read indication.
slave.
memory data.
of a received byte of data.
Communicating as a Master in a
Single Master Environment
2
C device address byte to the slave
DS39747C-page 123