PIC24FJ64GA006-I/PT Microchip Technology Inc., PIC24FJ64GA006-I/PT Datasheet - Page 56

• Manufacturer Part Number: PIC24FJ64GA006-I/PT
• Description: 64 PIN, 64KB FLASH, 8 KB RAM, 53 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA006-I/PT

• A/d Inputs: 16 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 53
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 53
• Number Of Pins: 64
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 16 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ128GA FAMILY
TABLE 5-3:
5.2.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has NOT expired (if
• The PLL has not achieved a LOCK (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
DS39747C-page 54
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
a crystal oscillator is used).
Reset Type
2:
3:
4:
5:
6:
T
T
regulator disabled.
T
T
oscillator clock to the system.
T
T
POR AND LONG OSCILLATOR
START-UP TIMES
STARTUP
OST
RST
POR
LOCK
FSCM
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Internal state Reset time (20 μs nominal).
= Power-on Reset delay (10 μs nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
EC, FRC, FRCDIV, LPRC T
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC, FRC, FRCDIV, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any clock
Any Clock
Any Clock
Any Clock
= PLL lock time (20 μs nominal).
= Fail-Safe Clock Monitor delay (100 μs nominal).
= T
Clock Source
VREG
(10 μs nominal) if on-chip regulator enabled or T
T
T
T
POR
POR
POR
POR
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
Preliminary
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
RST
RST
RST
RST
+ T
+ T
+ T
+ T
5.2.2
If the FSCM is enabled, it will begin to monitor the sys-
tem clock source when SYSRST is released. If a valid
clock source is not available at this time, the device will
automatically switch to the FRC oscillator and the user
can switch to the desired crystal oscillator in the Trap
Service Routine.
RST
RST
RST
RST
System Clock
T
T
OST
OST
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
T
T
Delay
T
T
LOCK
LOCK
+ T
+ T
OST
OST
—
—
—
—
—
—
—
—
PWRT
LOCK
LOCK
(64 ms nominal) if on-chip
© 2006 Microchip Technology Inc.
FSCM
T
T
T
T
T
T
Delay
FSCM
FSCM
FSCM
FSCM
FSCM
FSCM
—
—
—
—
—
—
—
—
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
2, 3
2, 3, 5, 6
2, 3, 4, 6
2, 3, 4, 5, 6
3
3
3
3
3
3
Notes