PIC18F2450-I/ML Microchip Technology Inc., PIC18F2450-I/ML Datasheet
PIC18F2450-I/ML
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PIC18F2450-I/ML Summary of contents
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... High-Performance, © 2006 Microchip Technology Inc. PIC18F2450/4450 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology Advance Information Data Sheet DS39760A ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Advance Information , microID, MPLAB, PIC, PICmicro, PICSTART, ® 8-bit MCUs ® code hopping EE OQ © 2006 Microchip Technology Inc. ...
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... Includes 256 bytes of dual access RAM used by USB module and shared with data memory. © 2006 Microchip Technology Inc. PIC18F2450/4450 Peripheral Highlights: • High-current sink/source: 25 mA/25 mA • Three external interrupts • Three Timer modules (Timer0 to Timer2) • Capture/Compare/PWM (CCP) module: - Capture is 16-bit, max ...
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... RA5/AN4/HLVDIN V OSC1/CLKI OSC2/CLKO/RA6 Note: Pinouts are subject to change. DS39760A-page 2 /RE3 REF REF USB RB3/AN9/VPO + 2 20 RB2/AN8/INT2/VMO 3 19 RB1/AN10/INT1 PIC18F2450 4 18 RB0/AN12/INT0 RC7/RX/ Advance Information RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1 RB0/AN12/INT0 RC7/RX/DT RC6/TX/CK RC5/D+/VP RC4/D-/ © 2006 Microchip Technology Inc. ...
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... RE2/AN7 V V OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/UOE RC2/CCP1 V USB RD0 RD1 44-Pin QFN RC7/RX/DT RD4 RD5 RD6 RD7 RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO Note: Pinouts are subject to change. © 2006 Microchip Technology Inc. PIC18F2450/4450 1 RB7/KBI3/PGD 40 RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 37 + RB3/AN9/VPO 5 36 RB2/AN8/INT2/VMO RB1/AN10/INT1 34 8 RB0/AN12/INT0 33 ...
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... PIC18F2450/4450 Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT RD4 RD5 RD6 RD7 RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO RB3/AN9/VPO Note: Pinouts are subject to change. * Assignment of this feature is dependent on device configuration. DS39760A-page 4 NC/ICRST*/ICV 1 33 RC0/T1OSO/T1CKI 2 32 OSC2/CLKO/RA6 31 3 OSC1/CLKI PIC18F4450 RE2/AN7 27 7 RE1/AN6 8 26 RE0/AN5 ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 305 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 305 Index ................................................................................................................................................................................................. 307 The Microchip Web Site ..................................................................................................................................................................... 315 Customer Change Notification Service .............................................................................................................................................. 315 Customer Support .............................................................................................................................................................................. 315 Reader Response .............................................................................................................................................................................. 316 PIC18F2450/4450 Product Identification System .............................................................................................................................. 317 © 2006 Microchip Technology Inc. PIC18F2450/4450 Advance Information DS39760A-page 5 ...
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... PIC18F2450/4450 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... Microchip Technology Inc. PIC18F2450/4450 1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2450/4450 family offer twelve different oscillator options, allowing users a wide range of choices in developing application hardware. These include: computational • Four Crystal modes using crystals or ceramic resonators. • ...
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... Like all Microchip PIC18 devices, members of the PIC18F2450/4450 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2450), accommodate an operating V range of 4.2V to 5.5V. Low-voltage parts, DD designated by “LF” (such as PIC18LF2450), function ...
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... Timers Capture/Compare/PWM Modules Enhanced USART Universal Serial Bus (USB) Module 10-bit Analog-to-Digital Module Resets (and Delays) Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages © 2006 Microchip Technology Inc. PIC18F2450/4450 PIC18F2450 DC – 48 MHz 16384 8192 768 13 Ports ( Input Channels POR, BOR, ...
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... PIC18F2450/4450 FIGURE 1-1: PIC18F2450 (28-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR (24/32 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction Decode & Control (2) Internal ...
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... Section 2.0 “Oscillator Configurations” for additional information. 3: These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 18.9 “Special ICPORT Features (Designated Packages Only)” for additional information. © 2006 Microchip Technology Inc. PIC18F2450/4450 Data Bus<8> Data Latch 8 8 ...
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... PIC18F2450/4450 TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP, QFN SOIC MCLR/Vpp/RE3 1 26 MCLR V PP RE3 OSC1/CLKI 9 6 OSC1 CLKI OSC2/CLKO/RA6 10 7 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39760A-page 12 ...
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... TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, QFN SOIC RA0/AN0 2 27 RA0 AN0 RA1/AN1 3 28 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI/RCV 6 3 RA4 T0CKI RCV RA5/AN4/HLVDIN 7 4 RA5 AN4 ...
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... PIC18F2450/4450 TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, QFN SOIC RB0/AN12/INT0 21 18 RB0 AN12 INT0 RB1/AN10/INT1 22 19 RB1 AN10 INT1 RB2/AN8/INT2/VMO 23 20 RB2 AN8 INT2 VMO RB3/AN9/VPO 24 21 RB3 AN9 VPO RB4/AN11/KBI0 25 22 RB4 AN11 KBI0 ...
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... TABLE 1-2: PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, QFN SOIC RC0/T1OSO/T1CKI 11 8 RC0 T1OSO T1CKI RC1/T1OSI/UOE 12 9 RC1 T1OSI UOE RC2/CCP1 13 10 RC2 CCP1 RC4/D-/ RC4 D- VM RC5/D+/ RC5 D+ VP RC6/TX/ RC6 TX CK RC7/RX/ RC7 RX DT RE3 — ...
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... PIC18F2450/4450 TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN TQFP MCLR/Vpp/RE3 1 18 MCLR V PP RE3 OSC1/CLKI 13 32 OSC1 CLKI OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: These pins are No Connect unless the ICPRT Configuration bit is set ...
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... Output Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... PIC18F2450/4450 TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RB0/AN12/INT0 33 9 RB0 AN12 INT0 RB1/AN10/INT1 34 10 RB1 AN10 INT1 RB2/AN8/INT2/VMO 35 11 RB2 AN8 INT2 VMO RB3/AN9/VPO 36 12 RB3 AN9 VPO RB4/AN11/KBI0 37 14 RB4 AN11 KBI0 ...
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... Output Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... PIC18F2450/4450 TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RD0 19 38 RD1 20 39 RD2 21 40 RD3 22 41 RD4 27 2 RD5 28 3 RD6 29 4 RD7 30 5 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... Output Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... PIC18F2450/4450 NOTES: DS39760A-page 22 Advance Information © 2006 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F2450/4450 2.2 Oscillator Types PIC18F2450/4450 devices can be operated in twelve distinct oscillator modes. In contrast with the non-USB PIC18 enhanced microcontrollers, four of these modes involve the use of two oscillator types at once. Users can program the FOSC3:FOSC0 Configuration bits to select one of these modes: 1 ...
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... With PIC18F2450/4450 devices, the primary oscillator becomes part of the USB module and cannot be associated to any other clock source. Thus, the USB module must be clocked from the primary clock source ...
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... See the notes following Table 2-2 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2006 Microchip Technology Inc. PIC18F2450/4450 TABLE 2-2: Osc Type XT HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... XT and HS modes is also available in EC and ECIO modes. DS39760A-page 26 2.2.4 PLL FREQUENCY MULTIPLIER PIC18F2450/4450 devices include a Phase Locked Loop (PLL) circuit. This is provided specifically for USB applications with lower speed oscillators and can also be used as a microcontroller clock source. The PLL is enabled in HSPLL, XTPLL, ECPLL and ECPIO Oscillator modes ...
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... INTERNAL OSCILLATOR The PIC18F2450/4450 devices include an internal RC oscillator (INTRC) which provides a nominal 31 kHz out- put. INTRC is enabled selected as the device clock source also enabled automatically when any of the following are enabled: • Power-up Timer • Fail-Safe Clock Monitor • Watchdog Timer • ...
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... PIC18F2450/4450 TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION Input Oscillator PLL Division Frequency (PLLDIV2:PLLDIV0) (1) 48 MHz N/A 48 MHz 12 (111) 40 MHz 10 (110) 24 MHz 6 (101) 20 MHz 5 (100) 16 MHz 4 (011) Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). ...
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... Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). Note 1: Only valid when the USBDIV Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Clock Mode MCU Clock Division (FOSC3:FOSC0) (CPUDIV1:CPUDIV0) ...
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... Switching Like previous PIC18 enhanced PIC18F2450/4450 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2450/4450 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available ...
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... Unimplemented: Read as ‘0’ bit 1-0 SCS1:SCS0: System Clock Select bits 1x = Internal oscillator 01 = Timer1 oscillator 00 = Primary oscillator Note 1: Depends on the state of the IESO Configuration bit. © 2006 Microchip Technology Inc. PIC18F2450/4450 (1) U-0 R U-0 — OSTS — Unimplemented bit, read as ‘0’ ...
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... PIC18F2450/4450 2.5 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. Unless the USB module is enabled, the OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating ...
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... POWER-MANAGED MODES PIC18F2450/4450 devices offer a total of seven operating modes for more efficient management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • Idle modes • ...
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... PIC18F2450/4450 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status. They are: • ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur dur- ing entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator, the use of RC_RUN mode is not recommended. © 2006 Microchip Technology Inc. PIC18F2450/4450 PLL (1) ...
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... PIC18F2450/4450 FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE INTRC OSC1 CPU Clock Peripheral Clock Program PC Counter Note 1: Clock transition typically occurs within 2-4 T FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 INTRC OSC1 OST (1) T PLL Clock Output CPU Clock Peripheral ...
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... Sleep Mode The power-managed Sleep mode in the PIC18F2450/ 4450 devices is identical to the legacy Sleep mode offered in all other PICmicro devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared ...
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... PIC18F2450/4450 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation, with its more accurate primary clock source, since the clock source does not have to “ ...
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... Section 8.0 “Interrupts”). © 2006 Microchip Technology Inc. PIC18F2450/4450 A fixed delay of interval T is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. ...
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... PIC18F2450/4450 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped; and • the primary clock source is not any of the modes ...
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... RESET The PIC18F2450/4450 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F2450/4450 REGISTER 4-1: RCON: RESET CONTROL REGISTER (1) R/W-0 R/W-1 U-0 IPEN SBOREN — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
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... The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2450/4450 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 9.5 “PORTE, TRISE and LATE Registers” ...
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... PIC18F2450/4450 4.4 Brown-out Reset (BOR) PIC18F2450/4450 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any values of BOREN1:BOREN0 except ‘ ...
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... Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of the PIC18F2450/4450 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 65.6 ms. While the PWRT is counting, the device is held in Reset. ...
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... PIC18F2450/4450 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the Power-up Timer. PLL © 2006 Microchip Technology Inc. PIC18F2450/4450 , V RISE > PWRT T OST T PWRT T OST T ...
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... PIC18F2450/4450 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2006 Microchip Technology Inc. PIC18F2450/4450 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2450/4450 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 2450 4450 POSTINC2 2450 4450 POSTDEC2 2450 4450 PREINC2 2450 4450 PLUSW2 2450 4450 FSR2H 2450 4450 FSR2L 2450 4450 STATUS 2450 4450 TMR0H 2450 4450 TMR0L 2450 ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2006 Microchip Technology Inc. PIC18F2450/4450 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2450/4450 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices UEP8 2450 4450 UEP7 2450 4450 UEP6 2450 4450 UEP5 2450 4450 UEP4 2450 4450 UEP3 2450 4450 UEP2 2450 4450 UEP1 2450 4450 UEP0 2450 4450 UCFG 2450 ...
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... NOP instruction). The PIC18F2450 and PIC18F4450 each have 16 Kbytes of Flash memory and can store up to 8192 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h ...
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... PIC18F2450/4450 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2006 Microchip Technology Inc. PIC18F2450/4450 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... PIC18F2450/4450 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2006 Microchip Technology Inc. PIC18F2450/4450 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... PIC18F2450/4450 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction ...
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... RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. PIC18F2450/ 4450 devices implement three complete banks, for a total of 768 bytes. Figure 5-5 shows the data memory organization for the devices ...
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... PIC18F2450/4450 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2450/4450 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh = 0101 00h Bank 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh Note 1: This bank also serve as RAM buffer for USB operation. See Section 5.3.1 “ ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2006 Microchip Technology Inc. PIC18F2450/4450 Data Memory 000h 7 00h ...
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... Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2450/4450 DEVICES Address Name Address Name ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450) File Name Bit 7 Bit 6 Bit 5 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... PIC18F2450/4450 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 OSCCON IDLEN — HLVDCON VDIRMAG — IRVST WDTCON — — (2) RCON IPEN SBOREN TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte T1CON RD16 T1RUN T1CKPS1 TMR2 ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 PORTC RC7 RC6 RC5 PORTB RB7 RB6 RB5 (4) PORTA — RA6 RA5 UEP15 — — UEP14 — — UEP13 — — UEP12 — — UEP11 — — UEP10 — ...
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... PIC18F2450/4450 5.3.6 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC bits, the results of the instruction are not written ...
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... Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.4 “General © 2006 Microchip Technology Inc. PIC18F2450/4450 Purpose Register File” location in the Access Bank (Section 5.3.3 “Access Bank”) as the data source for the instruction. ...
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... PIC18F2450/4450 5.4.3.1 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers: FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
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... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. © 2006 Microchip Technology Inc. PIC18F2450/4450 5.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations ...
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... PIC18F2450/4450 5.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds eight additional two-word commands to the existing PIC18 instruction set: ADDFSR, ADDULNK, CALLW, MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2006 Microchip Technology Inc. PIC18F2450/4450 000h 060h 080h Bank 0 100h Bank 1 through Bank 14 ...
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... PIC18F2450/4450 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower portion of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2006 Microchip Technology Inc. PIC18F2450/4450 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes DD between the program memory space and the data RAM: • ...
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... PIC18F2450/4450 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 16 holding registers, the address of which is determined by TBLPTRL<3:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
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... The WR bit can only be set (not cleared) in software Write cycle complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
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... PIC18F2450/4450 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
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... MOVF TABLAT, W MOVF WORD_ODD © 2006 Microchip Technology Inc. PIC18F2450/4450 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 80
... PIC18F2450/4450 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. When initiating an erase ...
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... Disable interrupts. 9. Write 55h to EECON2. © 2006 Microchip Technology Inc. PIC18F2450/4450 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
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... PIC18F2450/4450 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64’ MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA ...
Page 83
... PIE2 OSCFIE — USBIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access. © 2006 Microchip Technology Inc. PIC18F2450/4450 ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ...
Page 84
... PIC18F2450/4450 NOTES: DS39760A-page 82 Advance Information © 2006 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2006 Microchip Technology Inc. PIC18F2450/4450 EXAMPLE 7-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 7-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
Page 86
... PIC18F2450/4450 Example 7-3 shows the sequence unsigned multiplication. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 7- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 2 8 (ARG1H ARG2L 2 8 (ARG1L ARG2H 2 (ARG1L ARG2L) EXAMPLE 7-3: ...
Page 87
... INTERRUPTS The PIC18F2450/4450 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress ...
Page 88
... PIC18F2450/4450 FIGURE 8-1: INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP From USB USBIF Interrupt Logic USBIE USBIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit ...
Page 89
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
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... PIC18F2450/4450 REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 91
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-0 U-0 ...
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... PIC18F2450/4450 8.3 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
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... Unimplemented: Read as ‘0’ bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit high/low-voltage condition occurred high/low-voltage event has occurred bit 1-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/W-0 — — HLVDIF U = Unimplemented bit, read as ‘0’ ...
Page 94
... PIC18F2450/4450 8.4 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts ...
Page 95
... Unimplemented: Read as ‘0’ bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/W-0 — — HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 96
... PIC18F2450/4450 8.5 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 97
... Unimplemented: Read as ‘0’ bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/W-1 — — HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 98
... PIC18F2450/4450 8.6 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 8-10: RCON: RESET CONTROL REGISTER (1) R/W-0 ...
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... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2006 Microchip Technology Inc. PIC18F2450/4450 8.8 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2< ...
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... PIC18F2450/4450 NOTES: DS39760A-page 98 Advance Information © 2006 Microchip Technology Inc. ...
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... PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2006 Microchip Technology Inc. PIC18F2450/4450 Reading the PORTA register reads the status of the pins; writing to it will write to the port latch. The Data Latch register (LATA) is also memory mapped ...
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... PIC18F2450/4450 TABLE 9-1: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/ RA2 REF 1 AN2 REF RA3/AN3/ RA3 REF 1 AN3 REF RA4/T0CKI/ RA4 0 RCV 1 T0CKI 1 RCV x RA5/AN4/ RA5 0 HLVDIN 1 AN4 1 HLVDIN 1 OSC2 x OSC2/CLKO/ RA6 ...
Page 103
... MOVFF (ANY), PORTB instruction). This will end the mismatch condition. b) Clear flag bit, RBIF. © 2006 Microchip Technology Inc. PIC18F2450/4450 A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF cleared. The interrupt-on-change feature is recommended for ...
Page 104
... PIC18F2450/4450 TABLE 9-3: PORTB I/O SUMMARY TRIS Pin Function Setting RB0/AN12/ RB0 OUT 0 INT0 1 AN12 1 INT0 1 RB1/AN10/ RB1 OUT 0 INT1 1 AN10 1 INT1 1 RB2/AN8/ RB2 OUT 0 INT2/VMO 1 AN8 1 INT2 1 VMO OUT 0 RB3/AN9/VPO RB3 OUT 0 1 AN9 1 VPO OUT 0 RB4/AN11/ RB4 OUT 0 KBI0 ...
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... INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP ADCON1 — — UCON — PPBRST Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2006 Microchip Technology Inc. PIC18F2450/4450 Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 LATB3 ...
Page 106
... Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). In PIC18F2450/4450 devices, the RC3 pin is not implemented. The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC ...
Page 107
... Note 1: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is determined by the USB configuration. © 2006 Microchip Technology Inc. PIC18F2450/4450 I/O I/O Type OUT DIG LATC<0> data output. ...
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... PIC18F2450/4450 TABLE 9-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC7 LATC6 TRISC TRISC7 TRISC6 UCON — PPBRST Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0). ...
Page 109
... PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note Power-on Reset, these pins are configured as digital inputs. © 2006 Microchip Technology Inc. PIC18F2450/4450 EXAMPLE 9-4: CLRF PORTD CLRF LATD MOVLW 0CFh ...
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... PIC18F2450/4450 TABLE 9-7: PORTD I/O SUMMARY TRIS Pin Function Setting RD0 RD0 0 1 RD1 RD1 0 1 RD2 RD2 0 1 RD3 RD3 0 1 RD4 RD4 0 1 RD5 RD5 0 1 RD6 RD6 0 1 RD7 RD7 0 1 Legend: OUT = Output Input, DIG = Digital Output Schmitt Buffer Input ...
Page 111
... PORTE, TRISE and LATE Registers Depending on the particular PIC18F2450/4450 device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/AN5, RE1/AN6 and RE2/AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘ ...
Page 112
... PIC18F2450/4450 TABLE 9-9: PORTE I/O SUMMARY TRIS Pin Function Setting RE0/AN5 RE0 0 1 AN5 1 RE1/AN6 RE1 0 1 AN6 1 RE2/AN7 RE2 0 1 AN7 1 (1) MCLR/V / RE3 — PP RE3 (1) MCLR — (1) V — PP Legend: OUT = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input. ...
Page 113
... Prescale value 000 = 1:2 Prescale value © 2006 Microchip Technology Inc. PIC18F2450/4450 The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-Bit mode is shown in Figure 10-1. Figure 10-2 shows a simplified block diagram of the Timer0 module in 16- Bit mode ...
Page 114
... PIC18F2450/4450 10.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing (T0CON<5>). In Timer mode, the module increments on every clock by default unless a different prescaler value is selected (see Section 10.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register ...
Page 115
... Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. © 2006 Microchip Technology Inc. PIC18F2450/4450 10.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
Page 116
... PIC18F2450/4450 NOTES: DS39760A-page 114 Advance Information © 2006 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2006 Microchip Technology Inc. PIC18F2450/4450 A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 118
... PIC18F2450/4450 11.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 11-1: TIMER1 BLOCK DIAGRAM ...
Page 119
... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2006 Microchip Technology Inc. PIC18F2450/4450 TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 120
... PIC18F2450/4450 11.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 11-3, should be located as close as possible to the microcontroller. ...
Page 121
... RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2006 Microchip Technology Inc. PIC18F2450/4450 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 122
... PIC18F2450/4450 NOTES: DS39760A-page 120 Advance Information © 2006 Microchip Technology Inc. ...
Page 123
... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2006 Microchip Technology Inc. PIC18F2450/4450 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON< ...
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... PIC18F2450/4450 12.2 Timer2 Interrupt Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/ postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
Page 125
... CAPTURE/COMPARE/PWM (CCP) MODULE PIC18F2450/4450 devices have one CCP (Capture/ Compare/PWM) module. The module contains a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. REGISTER 13-1: CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER U-0 U-0 R/W-0 — ...
Page 126
... PIC18F2450/4450 13.1 CCP Module Configuration The Capture/Compare/PWM module is associated with a control register (generically, CCP1CON) and a data register (CCPR1). The data register, in turn, is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). All registers are both readable and writable. 13.1.1 ...
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... CCPR1H CCPR1L Compare Comparator TMR1H TMR1L © 2006 Microchip Technology Inc. PIC18F2450/4450 13.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP1M3:CCP1M0 = 1010), the CCP1 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP1IE bit is set. 13.3.4 ...
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... PIC18F2450/4450 TABLE 13-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (1) RCON IPEN SBOREN PIR1 — ADIF PIE1 — ADIE IPR1 — ADIP TRISC TRISC7 TRISC6 TMR1L Timer1 Register Low Byte TMR1H Timer1 Register High Byte T1CON ...
Page 129
... PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 © 2006 Microchip Technology Inc. PIC18F2450/4450 13.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: EQUATION 13-1: PWM Period = [(PR2 • 4 • T PWM frequency is defined as 1/[PWM period] ...
Page 130
... PIC18F2450/4450 The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. ...
Page 131
... USB Specification Revision 2.0 is the most current specification at the time of publication of this document. 14.1 Overview of the USB Peripheral The PIC18F2450/4450 device family contains a full- speed and low-speed compatible USB Serial Interface Engine (SIE) that allows fast communication between FIGURE 14-1: USB PERIPHERAL AND OPTIONS PIC18F2450/4450 Family 3 ...
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... PIC18F2450/4450 14.2 USB Status and Control The operation of the USB module is configured and managed through three control registers. In addition, a total of 22 registers are used to manage the actual USB transactions. The registers are: • USB Control register (UCON) • USB Configuration register (UCFG) • ...
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... Bus Speed (full speed versus low speed) • On-Chip Transceiver Enable • Ping-Pong Buffer Usage © 2006 Microchip Technology Inc. PIC18F2450/4450 The UCFG register also contains two bits which aid in module testing, debugging and USB certifications. These bits control output enable state monitoring and eye pattern generation ...
Page 134
... PIC18F2450/4450 REGISTER 14-2: UCFG: USB CONFIGURATION REGISTER R/W-0 R/W-0 U-0 (1) UTEYE UOEMON — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled ...
Page 135
... This line is pulled low by the device to enable the transmission of data from the SIE to an external device. 14.2.2.3 Pull-up Resistors The PIC18F2450/4450 devices require an external pull- up resistor to meet the requirements for low-speed and full-speed USB. Either an external 3.3V supply or the V pin may be used to pull D-. The pull-up USB resistor must be 1 ...
Page 136
... PIC18F2450/4450 14.2.3 USB STATUS REGISTER (USTAT) The USB Status register reports the transaction status within the SIE. When the SIE issues a USB transfer complete interrupt, USTAT should be read to determine the status of the transfer. USTAT contains the transfer endpoint number, direction and Ping-Pong Buffer Pointer value (if used) ...
Page 137
... EPSTALL: Endpoint Stall Enable bit 1 = Endpoint n is stalled 0 = Endpoint n is not stalled Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored. © 2006 Microchip Technology Inc. PIC18F2450/4450 transactions. For Endpoint 0, this bit should always be cleared since the Endpoint 0 as the default control endpoint. ...
Page 138
... PIC18F2450/4450 14.2.5 USB ADDRESS REGISTER (UADDR) The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written ...
Page 139
... UEPn register. All BD registers are available in USB RAM. The BD for each endpoint should be set up prior to enabling the endpoint. © 2006 Microchip Technology Inc. PIC18F2450/4450 14.4.1 BD STATUS AND CONFIGURATION Buffer descriptors not only define the size of an endpoint buffer, but also determine its configuration and control ...
Page 140
... PIC18F2450/4450 When UOWN is set, the user can no longer depend on the values that were written to the BDs. From this point, the SIE updates the BDs as necessary, overwriting the original BD values. The BDnSTAT register is updated by the SIE with the token PID and the transfer count, BDnCNT, is updated ...
Page 141
... This bit must be initialized by the user to the desired value prior to enabling the USB module. 2: This bit is ignored unless DTSEN = these bits are set, USB communication may not work. Hence, these bits should always be maintained as ‘0’. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-x R/W-x (3) — DTSEN U = Unimplemented bit, read as ‘0’ ...
Page 142
... PIC18F2450/4450 14.4.1.3 BDnSTAT Register (SIE Mode) When the BD and its buffer are owned by the SIE, most of the bits in BDnSTAT take on a different meaning. The configuration is shown in Register 14-6. Once UOWN is set, any data or control settings previously written there by the user will be overwritten with data from the SIE. ...
Page 143
... Maximum BDs: 32 (BD0 to BD31) Note: Memory area not shown to scale. © 2006 Microchip Technology Inc. PIC18F2450/4450 SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. The Even/Odd status of the last transaction is stored in the PPBI bit of the USTAT register ...
Page 144
... PIC18F2450/4450 TABLE 14-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES Mode 0 Endpoint (No Ping-Pong) Out Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer TABLE 14-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS Name Bit 7 Bit 6 (1) (4) BDnSTAT UOWN DTS (1) BDnCNT Byte Count (1) BDnADRL ...
Page 145
... The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. © 2006 Microchip Technology Inc. PIC18F2450/4450 Figure 14-8 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts ...
Page 146
... PIC18F2450/4450 14.5.1 USB INTERRUPT STATUS REGISTER (UIR) The USB Interrupt Status register (Register 14-7) contains the flag bits for each of the USB status interrupt sources. Each of these sources has a corresponding interrupt enable bit in the UIE register. All of the USB status flags are ORed together to generate the USBIF interrupt flag for the microcontroller’ ...
Page 147
... URSTIE: USB Reset Interrupt Enable bit 1 = USB Reset interrupt enabled 0 = USB Reset interrupt disabled © 2006 Microchip Technology Inc. PIC18F2450/4450 The values in this register only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt ...
Page 148
... PIC18F2450/4450 14.5.3 USB ERROR INTERRUPT STATUS REGISTER (UEIR) The USB Error Interrupt Status register (Register 14-9) contains the flag bits for each of the error sources within the USB peripheral. Each of these sources is controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic ...
Page 149
... PIDEE: PID Check Failure Interrupt Enable bit 1 = PID check failure interrupt enabled 0 = PID check failure interrupt disabled © 2006 Microchip Technology Inc. PIC18F2450/4450 As with the UIE register, the enable bits only affect the propagation of microcontroller’s interrupt logic. The flag bits are still ...
Page 150
... PIC18F2450/4450 14.6 USB Power Modes Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are Bus Power Only, Self-Power Only and Dual Power with Self-Power Dominance. The most common cases are presented here ...
Page 151
... This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 14-5. © 2006 Microchip Technology Inc. PIC18F2450/4450 Bit 5 Bit 4 ...
Page 152
... PIC18F2450/4450 14.9 Overview of USB This section presents some of the basic USB concepts and useful information necessary to design a USB device. Although much information is provided in this section, there is a plethora of information provided within the USB specifications and class specifications. Thus, the reader is encouraged to refer to the USB specifications for more information (www ...
Page 153
... There is only one device descriptor. © 2006 Microchip Technology Inc. PIC18F2450/4450 14.9.6.2 Configuration Descriptor The configuration descriptor provides information on the power requirements of the device and how many different interfaces are supported when in this configuration ...
Page 154
... PIC18F2450/4450 NOTES: DS39760A-page 152 Advance Information © 2006 Microchip Technology Inc. ...
Page 155
... Synchronous – Master (half-duplex) with selectable clock polarity • Synchronous – Slave (half-duplex) with selectable clock polarity © 2006 Microchip Technology Inc. PIC18F2450/4450 The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX EUSART: • bit SPEN (RCSTA<7>) must be set (= 1) • ...
Page 156
... PIC18F2450/4450 REGISTER 15-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 CSRC TX9 TXEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode Master mode (clock generated internally from BRG) ...
Page 157
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘ ...
Page 158
... PIC18F2450/4450 REGISTER 15-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 ABDOVF RCIDL — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) ...
Page 159
... EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2006 Microchip Technology Inc. PIC18F2450/4450 the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency ...
Page 160
... PIC18F2450/4450 TABLE 15-3: BAUD RATES FOR ASYNCHRONOUS MODES BAUD F = 40.000 MHz OSC RATE Actual SPBRG Actual (K) % Rate value Error (decimal) (K) 0.3 — — — 1.2 — — — 2.4 2.441 1.73 255 9.6 9.615 0.16 64 19.2 19.531 1.73 31 19.531 57.6 56.818 -1 ...
Page 161
... Microchip Technology Inc. PIC18F2450/4450 SYNC = 0, BRGH = 0, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (decimal) (K) 0.300 0.02 4165 0 ...
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... PIC18F2450/4450 15.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 15-1) begins whenever a Start bit is received and the ABDEN bit is set ...
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... Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. FIGURE 15-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX pin ABDOVF bit BRG Value XXXXh © 2006 Microchip Technology Inc. PIC18F2450/4450 Edge #1 Edge #2 Edge #3 bit 3 Start bit 1 bit 0 bit 2 bit 4 ...
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... PIC18F2450/4450 15.2 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses the standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is eight bits. ...
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... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. © 2006 Microchip Technology Inc. PIC18F2450/4450 bit 0 bit 1 Word 1 bit 0 bit 1 ...
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... PIC18F2450/4450 15.2.2 EUSART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 15-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate ...
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... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. © 2006 Microchip Technology Inc. PIC18F2450/4450 Start bit 0 bit 7/8 bit 7/8 ...
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... PIC18F2450/4450 15.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Therefore, the Baud Rate Generator is inactive and proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. ...
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... Reg. Empty Flag) SENDB sampled here SENDB (Transmit Shift Reg. Empty Flag) © 2006 Microchip Technology Inc. PIC18F2450/4450 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. ...
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... PIC18F2450/4450 15.3 EUSART Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA< ...
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... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. © 2006 Microchip Technology Inc. PIC18F2450/4450 bit 0 bit 2 bit 1 Bit 5 Bit 4 ...
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... PIC18F2450/4450 15.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RX pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. ...
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... SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. © 2006 Microchip Technology Inc. PIC18F2450/4450 To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC ...
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... PIC18F2450/4450 15.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode ...
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... These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. © 2006 Microchip Technology Inc. PIC18F2450/4450 The ADCON0 register, shown in Register 16-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 16-2, configures the functions of the port pins ...
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... PIC18F2450/4450 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 — — VCFG0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG0: Voltage Reference Configuration bit ( (AN2) REF bit 4 VCFG0: Voltage Reference Configuration bit (V ...
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... OSC Note 1: If the A/D F clock source is selected, a delay of one T RC clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-0 R/W-0 ACQT1 ACQT0 ADCS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F2450/4450 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (V and the voltage level on the RA3/AN3 and RA2/AN2/V - pins. REF REF The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D’ ...
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... Sampling Switch C = Sample/hold Capacitance (from DAC) HOLD R = Sampling Switch Resistance SS © 2006 Microchip Technology Inc. PIC18F2450/4450 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 6. Read A/D Result registers (ADRESH:ADRESL); ...
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... PIC18F2450/4450 16.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 16-3. The source impedance (R ) and the internal sampling ...
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... For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power devices only. © 2006 Microchip Technology Inc. PIC18F2450/4450 16.3 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as T ...
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... PIC18F2450/4450 16.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode ...
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... Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) © 2006 Microchip Technology Inc. PIC18F2450/4450 After the A/D conversion is completed or aborted wait is required before the next acquisition can be AD started. After this wait, acquisition on the selected channel is automatically started. ...
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... PIC18F2450/4450 16.8 Use of the CCP1 Trigger An A/D conversion can be started by the Special Event Trigger of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the ...
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... HIGH/LOW-VOLTAGE DETECT (HLVD) PIC18F2450/4450 devices have a High/Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is ...
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... PIC18F2450/4450 The module is enabled by setting the HLVDEN bit. Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. ...
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... Enable HLVD IRVST Internal Reference is stable © 2006 Microchip Technology Inc. PIC18F2450/4450 Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked ...
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... PIC18F2450/4450 FIGURE 17-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = CASE 1: HLVDIF may not be set V DD HLVDIF Enable HLVD IRVST CASE HLVDIF Enable HLVD IRVST Internal Reference is stable 17.5 Applications In many applications, the ability to detect a drop below or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach ...
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... OSCFIP — Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. © 2006 Microchip Technology Inc. PIC18F2450/4450 17.7 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. ...
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... PIC18F2450/4450 NOTES: DS39760A-page 188 Advance Information © 2006 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F2450/4450 In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2450/4450 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up ...
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... PIC18F2450/4450 18.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes ...
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... Divide by 5 (20 MHz oscillator input) 011 = Divide by 4 (16 MHz oscillator input) 010 = Divide by 3 (12 MHz oscillator input) 001 = Divide MHz oscillator input) 000 = No prescale (4 MHz oscillator input drives PLL directly) © 2006 Microchip Technology Inc. PIC18F2450/4450 R/P-0 R/P-0 R/P-1 CPUDIV1 CPUDIV0 PLLDIV2 U = Unimplemented bit, read as ‘ ...
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... PIC18F2450/4450 REGISTER 18-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 IESO FCMEN — bit 7 Legend Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 ...
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... PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section 21.0 “Electrical Characteristics” for the specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/P-1 R/P-1 R/P-1 (1) (1) BORV1 BORV0 BOREN1 U = Unimplemented bit, read as ‘ ...
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... PIC18F2450/4450 REGISTER 18-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 — — — bit 7 Legend Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 ...
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... ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/P-0 — — LPT1OSC U = Unimplemented bit, read as ‘ ...
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... PIC18F2450/4450 REGISTER 18-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 R/P-0 DEBUG XINST ICPRT bit 7 Legend Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ...
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... CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) or (000000-000FFFh) is not code-protected 0 = Boot block (000000-0007FFh) or (000000-000FFFh) is code-protected bit 5-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ...
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... PIC18F2450/4450 REGISTER 18-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 — — — bit 7 Legend Readable bit C = Clearable bit -n = Value when device is unprogrammed bit 7-2 Unimplemented: Read as ‘0’ bit 1 WRT1: Write Protection bit 1 = Block 1 (002000-003FFFh) is not write-protected ...