PIC18F2450-I/ML Microchip Technology Inc., PIC18F2450-I/ML Datasheet - Page 184

• Manufacturer Part Number: PIC18F2450-I/ML
• Description: Microcontroller; 16 KB Flash; 768 RAM; 0 EEPROM; 23 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2450-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Cpu Speed: 12 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 23
• Interface: EUSART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 2-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2450/4450
16.8
An A/D conversion can be started by the Special Event
Trigger of the CCP1 module. This requires that the
CCP1M3:CCP1M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 counter will be reset to
zero. Timer1 is reset to automatically repeat the A/D
acquisition period with minimal software overhead
TABLE 16-2:
DS39760A-page 182
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(4)
2:
3:
4:
(4)
Use of the CCP1 Trigger
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
These registers and/or bits are not implemented on 28-pin devices.
A/D Result Register High Byte
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register Low Byte
OSCFIE
OSCFIP
OSCFIF
TRISB7
LATB7
ADFM
Bit 7
RB7
—
—
—
—
—
—
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
bits
TRISA6
TRISB6
LATB6
RA6
ADIE
ADIP
ADIF
Bit 6
RB6
—
—
—
—
—
—
—
—
—
(CCP1CON<3:0>)
(2)
(2)
TRISA5
TRISB5
VCFG1
ACQT2
USBIF
USBIE
USBIP
LATB5
CHS3
RCIE
RCIP
RCIF
Bit 5
RA5
RB5
—
—
—
Advance Information
TRISA4
TRISB4
VCFG0
ACQT1
INT0IE
LATB4
CHS2
TXIE
TXIP
Bit 4
TXIF
be
RA4
RB4
—
—
—
—
—
—
TRISA3
TRISB3
RE3
PCFG3
ACQT0
LATB3
CHS1
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module but will still reset the Timer1 counter.
RBIE
Bit 3
RA3
RB3
—
—
—
—
—
—
—
—
(1,3)
TRISE2
LATE2
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
TRISA2
TRISB2
PCFG2
ADCS2
LATB2
RE2
CHS0
Bit 2
RA2
RB2
(4)
(4)
(4)
GO/DONE
TRISE1
LATE1
TMR2IF
TMR2IE
TMR2IP
TRISA1
TRISB1
PCFG1
ADCS1
INT0IF
LATB1
RE1
Bit 1
© 2006 Microchip Technology Inc.
RA1
RB1
—
—
—
(4)
(4)
ACQ
(4)
TRISE0
LATE0
time selected before
TMR1IF
TMR1IE
TMR1IP
TRISA0
TRISB0
PCFG0
ADCS0
LATB0
RE0
ADON
RBIF
Bit 0
RA0
RB0
—
—
—
(4)
(4)
(4)
on page
Values
Reset
49
51
51
51
51
51
51
50
50
50
50
50
51
51
51
51
51
51
51
51