PIC18F2450-I/ML Microchip Technology Inc., PIC18F2450-I/ML Datasheet - Page 76
PIC18F2450-I/ML
Manufacturer Part Number
PIC18F2450-I/ML
Description
Microcontroller; 16 KB Flash; 768 RAM; 0 EEPROM; 23 I/O; 28-Pin-QFN
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2450-IML.pdf
(320 pages)
Specifications of PIC18F2450-I/ML
A/d Inputs
10-Channel, 10-Bit
Cpu Speed
12 MIPS
Eeprom Memory
0 Bytes
Input Output
23
Interface
EUSART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
48 MHz
Timers
1-8-bit, 2-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2450-I/ML
Manufacturer:
TOSHIBA
Quantity:
2 000
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PIC18F2450/4450
FIGURE 6-2:
6.2
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
6.2.1
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory
EECON2 will read all ‘0’s.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory.
DS39760A-page 74
Control Registers
Note 1:
write
TBLPTRU
EECON1 AND EECON2 REGISTERS
and
Table Pointer
Table Pointer actually points to one of 16 holding registers, the address of which is determined by
TBLPTRL<3:0>. The process for physically writing data to the program memory array is discussed
in Section 6.5 “Writing to Flash Program Memory”.
TABLE WRITE OPERATION
TBLPTRH
erase
sequences.
(1)
TBLPTRL
Program Memory
(TBLPTR)
Advance Information
Reading
Instruction: TBLWT*
Holding Registers
Program Memory
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset or a write operation was
attempted improperly.
© 2006 Microchip Technology Inc.
Table Latch (8-bit)
TABLAT
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