PIC18F2450-I/ML Microchip Technology Inc., PIC18F2450-I/ML Datasheet - Page 77

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PIC18F2450-I/ML

Manufacturer Part Number
PIC18F2450-I/ML
Description
Microcontroller; 16 KB Flash; 768 RAM; 0 EEPROM; 23 I/O; 28-Pin-QFN
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F2450-I/ML

A/d Inputs
10-Channel, 10-Bit
Cpu Speed
12 MIPS
Eeprom Memory
0 Bytes
Input Output
23
Interface
EUSART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
48 MHz
Timers
1-8-bit, 2-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2450-I/ML
Manufacturer:
TOSHIBA
Quantity:
2 000
REGISTER 6-1:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition.
Unimplemented: Read as ‘0’
CFGS: Flash Program or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write-only
WRERR: Flash Program Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
0 = The write operation completed
WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program
0 = Inhibits write cycles to Flash program
WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
0 = Write cycle complete
Unimplemented: Read as ‘0’
R/W-x
CFGS
(cleared by completion of erase operation)
operation or an improper write attempt)
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
EECON1: MEMORY CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
U-0
Advance Information
R/W-0
FREE
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WRERR
R/W-x
(1)
PIC18F2450/4450
WREN
R/W-0
x = Bit is unknown
R/S-0
WR
DS39760A-page 75
U-0
bit 0

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