PIC18F2450-I/ML Microchip Technology Inc., PIC18F2450-I/ML Datasheet - Page 238

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PIC18F2450-I/ML

Manufacturer Part Number
PIC18F2450-I/ML
Description
Microcontroller; 16 KB Flash; 768 RAM; 0 EEPROM; 23 I/O; 28-Pin-QFN
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F2450-I/ML

A/d Inputs
10-Channel, 10-Bit
Cpu Speed
12 MIPS
Eeprom Memory
0 Bytes
Input Output
23
Interface
EUSART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
48 MHz
Timers
1-8-bit, 2-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2450-I/ML
Manufacturer:
TOSHIBA
Quantity:
2 000
PIC18F2450/4450
MOVFF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
DS39760A-page 236
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
REG1
REG2
REG1
REG2
Q1
No dummy
register ‘f’
operation
Move f to f
MOVFF f
0
0
(f
None
The contents of source register ‘f
moved to destination register ‘f
Location of source ‘f
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
2
2
MOVFF
s
Read
(src)
read
)
1100
1111
No
Q2
f
f
=
=
=
=
s
d
f
d
4095
4095
33h
11h
33h
33h
s
REG1, REG2
,f
ffff
ffff
d
operation
Process
Data
No
Q3
s
’ can be anywhere
ffff
ffff
register ‘f’
Advance Information
operation
(dest)
Write
d
No
Q4
ffff
ffff
’.
s
’ are
d
s
d
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
BSR Register =
BSR Register =
Q1
Move Literal to Low Nibble in BSR
MOVLW k
0
k
None
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’
regardless of the value of k
1
1
literal ‘k’
MOVLB
Read
0000
Q2
k
BSR
© 2006 Microchip Technology Inc.
255
02h
05h
0001
Process
5
Data
Q3
kkkk
Write literal
7
‘k’ to BSR
:k
4
.
Q4
kkkk

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