PIC18F2450-I/ML Microchip Technology Inc., PIC18F2450-I/ML Datasheet - Page 42

• Manufacturer Part Number: PIC18F2450-I/ML
• Description: Microcontroller; 16 KB Flash; 768 RAM; 0 EEPROM; 23 I/O; 28-Pin-QFN
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2450-I/ML

• A/d Inputs: 10-Channel, 10-Bit
• Cpu Speed: 12 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 23
• Interface: EUSART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 2-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2450/4450
3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
• the primary clock source is not any of the XT or
TABLE 3-2:
DS39760A-page 40
Note 1:
is not stopped; and
HS modes.
Primary Device Clock
T1OSC or INTRC
2:
3:
4:
(PRI_IDLE mode)
Before Wake-up
(Sleep mode)
In this instance, refers specifically to the 31 kHz INTRC clock source.
T
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
T
(parameter F12, Table 21-7); it is also designated as T
Execution continues during T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
INTRC
CSD
OST
None
(parameter 38, Table 21-10) is a required delay when waking from Sleep and all Idle modes and runs
is the Oscillator Start-up Timer period (parameter 32, Table 21-10). t
Microcontroller Clock Source
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(1)
(1)
IOBST
After Wake-up
XTPLL, HSPLL
XTPLL, HSPLL
XTPLL, HSPLL
XTPLL, HSPLL
Advance Information
INTRC
INTRC
INTRC
INTRC
XT, HS
XT, HS
XT, HS
XT, HS
(parameter 39, Table 21-10), the INTRC stabilization period.
EC
EC
EC
EC
(1)
(1)
(1)
(1)
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC and any internal
oscillator modes). However, a fixed delay of interval
T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
CSD
PLL
.
following the wake event is still required when
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
IOBST (4)
IOBST
None
None
CSD
CSD
CSD (2)
OST (3)
OST (3)
OST (3)
+ t
+ t
+ t
(2)
(2)
rc
rc
rc
(4)
(3)
(3)
(3)
rc
is the PLL lock time-out
© 2006 Microchip Technology Inc.
Clock Ready Status
Bit (OSCCON)
OSTS
OSTS
OSTS
OSTS