PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 200

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2220/2320/4220/4320
18.2
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free-running 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA<2>) also con-
trols the baud rate. In Synchronous mode, bit BRGH is
ignored. Table 18-1 shows the formula for computation
of the baud rate for different USART modes which only
apply in Master mode (internal clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
• F
• Desired Baud Rate = 9600
• BRGH = 0
• SYNC = 0
EXAMPLE 18-1:
TABLE 18-1:
TABLE 18-2:
DS39599C-page 198
0 (Asynchronous)
1 (Synchronous)
Legend: X = value in SPBRG (0 to 255)
TXSTA
RCSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Desired Baud Rate
Solving for X:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
Desired Baud Rate
Name
OSC
SYNC
= 16 MHz
USART Baud Rate Generator (BRG)
Baud Rate Generator Register
CSRC
SPEN
Bit 7
X
X
X
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
CALCULATING BAUD RATE ERROR
= F
= ((F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)
= (9615 – 9600)/9600
= 0.16%
Bit 6
RX9
TX9
OSC
OSC
Baud Rate = F
Baud Rate = F
/(64 (X + 1))
BRGH = 0 (Low Speed)
SREN
/Desired Baud Rate)/64) – 1
TXEN
Bit 5
OSC
, the nearest
CREN
SYNC
Bit 4
OSC
OSC
/(64 (X + 1))
/(4 (X + 1))
ADDEN
Bit 3
—
BRGH
FERR
Bit 2
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks, because the
F
error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
18.2.1
The system clock is used to generate the desired baud
rate; however, when a power managed mode is
entered, the clock source may be operating at a differ-
ent frequency than in PRI_RUN mode. In Sleep mode,
no clocks are present and in PRI_IDLE, the primary
clock source continues to provide clocks to the baud
rate generator; however, in other power managed
modes, the clock frequency will probably change. This
may require the value in SPBRG to be adjusted.
18.2.2
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
OSC
/(16 (X + 1)) equation can reduce the baud rate
OERR
TRMT
Bit 1
POWER MANAGED MODE
OPERATION
SAMPLING
Baud Rate = F
RX9D
TX9D
Bit 0
BRGH = 1 (High Speed)
 2003 Microchip Technology Inc.
0000 -010
0000 -00x
0000 0000
POR, BOR
Value on
N/A
OSC
/(16 (X + 1))
0000 -010
0000 -00x
0000 0000
Value on
all other
Resets