PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 221

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

19.7
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Sleep mode before the
conversion begins.
Figure 19-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are set to ‘010’ and selecting a 4 T
time before the conversion starts.
FIGURE 19-3:
FIGURE 19-4:
 2003 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO bit
1
T
Set GO bit
CY
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
T
Automatic
Acquisition
Time
ACQT
- T
2
AD
Conversion starts
Cycles
T
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
Conversion starts
(Holding capacitor is disconnected)
AD
b8
1
3 T
AD
b9
b7
2
AD
Next Q4: ADRESH/ADRESL are loaded, GO bit is cleared,
4 T
Next Q4: ADRESH:ADRESL are loaded, GO bit is cleared,
acquisition
PIC18F2220/2320/4220/4320
AD
b8
b6
3
AD
AD
5 T
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (A
CYCLES (A
ADIF bit is set, holding capacitor is reconnected to analog input.
AD
b5
4
b7
6 T
AD
T
b4
5
b6
AD
7 T
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
Cycles
CQT
CQT
AD
Note:
b3
b5
AD
6
8
<2:0> = 000, T
<2:0> = 010, T
wait is required before the next acquisition can
T
AD
b2
b4
7
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
AD
b3
b1
8
10
T
AD
ACQ
b0
b2
ACQ
9
11
= 0)
= 4 T
10
b1
AD
DS39599C-page 219
b0
11
)